PLL Loop Filter Design: Second- and Third-Order Passive Filters

PLL loop filter design is the process of choosing the resistor and capacitor values between the charge pump and the VCO so that the phase-locked loop has a chosen bandwidth and phase margin. To design one, set the loop bandwidth from the phase noise and lock-time targets, pick a phase margin of about 45° to 60°, compute the filter’s zero and pole time constants, and then solve for the components from the charge pump current, VCO gain and divide ratio.

The loop filter sets how fast the loop locks, how much reference spur leaks through and where the output phase noise changes from PLL-dominated to VCO-dominated. This page covers the passive second- and third-order filters used with charge-pump PLLs, with a worked 2.4 GHz design. The architecture is introduced in PLLs, frequency synthesis and phase noise, part of the oscillators and frequency synthesis section of the RF design guide.

The Loop and Its Open-Loop Gain

In a charge-pump PLL the phase-frequency detector (PFD) compares the reference with the divided VCO output and switches a charge pump of current I_CP. The phase detector gain is K_φ = I_CP/2π in amperes per radian. The loop filter converts that current into a tuning voltage through its transimpedance Z(s), and the VCO converts voltage into frequency with gain K_VCO, or K_v = 2πK_VCO in rad/s per volt. Because the VCO integrates frequency into phase, the open-loop gain is

G(s) = K_φ K_v Z(s) / (N s)

where N is the feedback divide ratio. The loop bandwidth is usually defined as the frequency f_c where |G| = 1, and the phase margin is 180° plus the phase of G at that frequency. The closed-loop transfer from the reference to the output is N·G/(1 + G), and from VCO noise to the output it is 1/(1 + G). That pair of transfer functions is why the bandwidth decides the phase noise profile.

Charge-pump PLL block diagram with reference, PFD, charge pump, third-order RC loop filter, VCO and divider — Figure 1: Charge-pump PLL with a third-order passive loop filter (schematic only). The example uses a 10 MHz reference, 2.5 mA charge pump, 50 MHz/V VCO and N = 240.

Second-Order Passive Loop Filter Equations

The basic passive filter is a shunt capacitor C₁ in parallel with a series branch R₂–C₂. Its transimpedance is

Z(s) = (1 + sT₂) / [ s(C₁ + C₂)(1 + sT₁) ], with T₂ = R₂C₂ and T₁ = R₂C₁C₂/(C₁ + C₂)

The integrator 1/s gives the loop a second integration (a type 2 loop), so it settles with zero static phase error. The zero at 1/T₂ provides phase lead for stability, and the pole at 1/T₁ smooths the charge pump pulses. Maximum phase margin occurs at the geometric mean of the zero and pole, so the design places f_c there:

T₁ = (sec φ − tan φ)/ω_c, where φ is the target phase margin
T₂ = 1/(ω_c²T₁)
C₁ + C₂ = (K_φK_v/(Nω_c²)) × √[(1 + ω_c²T₂²)/(1 + ω_c²T₁²)]
C₁ = (C₁ + C₂)T₁/T₂, C₂ = (C₁ + C₂) − C₁, R₂ = T₂/C₂

The third equation is simply |G(jω_c)| = 1 solved for the total capacitance.

Third-Order Passive Loop Filter Equations

A second-order filter passes a significant fraction of the charge pump ripple at the PFD frequency, which modulates the VCO and produces reference spurs at f_out ± f_PFD. Adding a series R₃ and shunt C₃ in front of the VCO creates a third pole at 1/T₃ that attenuates those spurs further. The transimpedance becomes

Z(s) = (1 + sT₂) / [ s(A₂s² + A₁s + A₀) ]

with A₀ = C₁ + C₂ + C₃, A₁ = C₂R₂(C₁ + C₃) + C₃R₃(C₁ + C₂) and A₂ = C₁C₂C₃R₂R₃. The denominator factors as A₀(1 + sT₁)(1 + sT₃), so A₁ = A₀(T₁ + T₃) and A₂ = A₀T₁T₃. A widely used procedure, set out in Banerjee’s PLL design text, runs as follows:

Choose the pole ratio T₃/T₁, commonly around 0.25. Larger values give more spur attenuation and less phase margin to work with.
Solve numerically for T₁ so that the phase margin tan⁻¹(ω_cT₂) − tan⁻¹(ω_cT₁) − tan⁻¹(ω_cT₃) equals the target, with T₂ = 1/(ω_c²(T₁ + T₃)).
Set A₀ = (K_φK_v/(Nω_c²)) × √[(1 + ω_c²T₂²)/((1 + ω_c²T₁²)(1 + ω_c²T₃²))], then A₁ and A₂ from the time constants.
Solve for the components: C₁ = (A₂/T₂²)[1 + √(1 + (T₂/A₂)(T₂A₀ − A₁))], C₃ = (−T₂²C₁² + T₂A₁C₁ − A₂A₀)/(T₂²C₁ − A₂), C₂ = A₀ − C₁ − C₃, R₂ = T₂/C₂ and R₃ = A₂/(C₁C₃T₂).
Round to standard values and recheck f_c and phase margin by evaluating G(jω) from the actual components.

Worked Example: 2.4 GHz Synthesizer

Design a filter for a 2.4 GHz output from a 10 MHz PFD (N = 240), with I_CP = 2.5 mA, K_VCO = 50 MHz/V, f_c = 40 kHz and a 50° phase margin. Then K_φ = 2.5 mA/2π = 0.398 mA/rad and ω_c = 2.513 × 10⁵ rad/s.

Open-loop gain magnitude and phase of second and third order loop filter designs crossing 0 dB at 40 kHz — Figure 2: Open-loop gain of the worked example. Both designs cross 0 dB at 40 kHz with 50° phase margin; the third-order filter rolls off faster above a few hundred kilohertz.

Second-order design: sec 50° − tan 50° = 1.5557 − 1.1918 = 0.3640, so T₁ = 1.448 µs and T₂ = 10.93 µs. The zero is at 14.6 kHz and the pole at 109.9 kHz, with 40 kHz at their geometric mean. The capacitance equation gives C₁ = 3.00 nF, C₂ = 19.65 nF and R₂ = 556 Ω.

Third-order design with T₃ = 0.25T₁: solving for 50° gives T₁ = 1.146 µs, T₃ = 0.287 µs and T₂ = 11.05 µs (zero at 14.4 kHz, poles at 138.8 kHz and 555 kHz). The component equations give the values below.

Component	Calculated	Standard value
C₁	1.19 nF	1.2 nF
C₂	21.5 nF	22 nF
R₂	514 Ω	510 Ω
R₃	910 Ω	910 Ω
C₃	638 pF	680 pF

Evaluating G(jω) with the standard values gives f_c = 39.6 kHz and a phase margin of 49.6°, close enough to the target. At the 10 MHz PFD frequency the filter transimpedance falls from 5.30 Ω for the second-order design to 0.365 Ω for the third-order design, so the third pole buys about 23 dB of extra reference-spur attenuation with no change to the loop dynamics near f_c. A linear simulation of the closed loop shows a 1 MHz output frequency step settling to within 1 kHz in about 38 µs, with 28 percent overshoot. Large steps can cycle-slip and take longer.

Phase Margin and Closed-Loop Peaking

Phase margin trades settling speed against stability and noise peaking. With the same 40 kHz crossover, the third-order design peaks by 6.0 dB at 30° margin, 3.2 dB at 45°, 2.6 dB at 50°, 1.7 dB at 60° and 1.1 dB at 70°. Peaking amplifies in-band noise near the loop bandwidth, and low margins ring longer after a frequency step. Most designs use 45° to 60°.

Closed-loop response for 30, 50 and 70 degree phase margin showing 6.0, 2.6 and 1.1 dB peaking — Figure 3: Closed-loop response at 40 kHz crossover. Peaking is 6.0 dB at 30° phase margin, 2.6 dB at 50° and 1.1 dB at 70°.

K_VCO often varies by a factor of two across the tuning range, and f_c scales roughly with it, so design at the midpoint, check both ends, and adjust the charge pump current where the PLL IC allows.

Loop Bandwidth vs Phase Noise

Inside the loop bandwidth the output follows the reference and the PLL’s own noise, multiplied by N. Outside it the output follows the free-running VCO. The in-band floor of a PLL IC is often estimated from a normalized figure of merit:

L_in-band ≈ FOM + 10log₁₀(f_PFD) + 20log₁₀(N)

Assuming FOM = −220 dBc/Hz, a value representative of many modern integer-N parts, the example gives −220 + 70 + 47.6 = −102.4 dBc/Hz. If the VCO is −110 dBc/Hz at 100 kHz offset and falls at 20 dB per decade, the two curves cross at 100 kHz × 10^{(−110 + 102.4)/20} = 41.7 kHz. Setting the loop bandwidth near this crossover usually minimizes integrated phase noise. Integrating the modelled output from 1 kHz to 10 MHz confirms it:

Loop bandwidth	Phase noise at 10 kHz	at 100 kHz	Integrated (1 kHz to 10 MHz)	RMS jitter at 2.4 GHz
10 kHz	−88.3 dBc/Hz	−109.8 dBc/Hz	0.42° rms	485 fs
40 kHz	−99.9 dBc/Hz	−105.7 dBc/Hz	0.28° rms	327 fs
150 kHz	−102.3 dBc/Hz	−99.6 dBc/Hz	0.39° rms	456 fs

A narrow loop lets VCO noise through close to the carrier; a wide loop passes the PLL floor out to offsets where the VCO would have been quieter. The model ignores resistor thermal noise, reference noise and PLL 1/f noise, which a full simulation should include. EVM depends on integrated noise, while reciprocal mixing depends on the noise at the offset of the nearest blocker. Measured results can be checked as described in phase noise measurement.

Modelled output phase noise for 10, 40 and 150 kHz loop bandwidths with PLL floor and free-running VCO — Figure 4: Modelled phase noise at 2.4 GHz with a −102.4 dBc/Hz in-band floor. The 40 kHz loop, near the 41.7 kHz crossover, gives the lowest integrated noise (0.28° rms).

Practical Design Checklist

Keep f_c below roughly f_PFD/10; the continuous-time analysis becomes inaccurate closer to the PFD rate.
Prefer C0G/NP0 or film capacitors; high-K ceramics change value with bias and temperature and some are microphonic.
A passive filter cannot drive the VCO beyond the charge pump supply; use an active filter when the tuning range needs more.
Keep the high-impedance tuning node short and away from digital lines.

Frequently Asked Questions

How do you design a PLL loop filter?

Choose the loop bandwidth and phase margin, compute the zero and pole time constants so maximum phase lead falls at the bandwidth, then solve for the capacitance that makes the open-loop gain equal to one there. Divide that into C₁, C₂ and R₂ (plus R₃ and C₃ for a third-order filter), round to standard values and recheck the margin.

What phase margin should a PLL have?

Between about 45° and 60° is typical. Below about 40° the closed-loop response peaks by several decibels and settling rings; above about 70° the loop gets slower for the same bandwidth.

How wide should the loop bandwidth be?

For lowest integrated phase noise, near the offset where the PLL in-band noise equals the free-running VCO noise. Lock time pushes it wider; spur suppression pushes it narrower.

When is a third-order filter needed?

When reference spurs from the second-order design are too high. The extra RC pole, typically placed four to five times above the main pole, attenuates ripple at the PFD frequency.