Direct Digital Synthesis (DDS)

Direct digital synthesis (DDS) is a frequency synthesis method that generates a sine wave digitally. A phase accumulator advances by a programmable tuning word on every clock cycle, a lookup table converts the phase to amplitude, and a DAC turns the samples into an analog waveform. Unlike a PLL, it has no feedback loop, so it can change frequency in a single clock cycle with sub-hertz resolution.

The price is a spectrum that is never perfectly clean. Phase truncation, amplitude quantization and DAC nonlinearity produce spurs, the DAC’s zero-order hold imposes a sinc-shaped roll-off, and images of the output appear around every multiple of the clock. This page explains how each part of a DDS works, derives the frequency and spur formulas, and works through a numerical example. It belongs to the oscillators and frequency synthesis section of the RF design map.

How DDS Works

A DDS has four blocks, all clocked by a fixed reference at f_clk:

Phase accumulator: an N-bit register and adder. On each clock edge the tuning word M is added to the register, which wraps around modulo 2^N. The register value is the instantaneous phase, with 2^N representing one full cycle.
Phase-to-amplitude converter: the top P bits of the accumulator address a sine lookup table, or drive an equivalent algorithm such as CORDIC. Symmetry lets the table store only a quarter cycle.
DAC: a D-bit converter turns the amplitude codes into a stepped analog waveform. Its behaviour is covered in Radio Architectures Part 11.
Reconstruction filter: a low-pass or band-pass filter removes the images above f_clk/2 and leaves a smooth sine.

Because the only analog parts are the DAC and filter, the output frequency, phase and amplitude are all set numerically. Many DDS devices add a phase offset register and an amplitude multiplier, which makes phase-coherent switching, PSK and FSK modulation, and linear frequency chirps straightforward.

Block diagram of a DDS: tuning word, phase accumulator, lookup table, DAC and low-pass filter with a common clock — Figure 1: DDS signal chain. The accumulator adds M every clock cycle and the top P bits address the sine table (schematic only).

The Phase Accumulator

The accumulator overflows once every 2^N/M clock cycles on average, so the output frequency and resolution are

f_out = M · f_clk / 2^N Δf = f_clk / 2^N

Figure 2 shows a deliberately short 8-bit accumulator with M = 19. The register ramps up in steps of 19 and wraps at 256, giving f_out = 19/256 × f_clk = 0.0742 f_clk. The wrap points do not fall at the same place in each cycle, because 256 is not a multiple of 19. The sine samples are still exact points on the ideal waveform; only the phase at which each sample is taken varies.

Staircase ramp of an 8-bit phase accumulator with tuning word 19 and the resulting sine samples — Figure 2: An 8-bit accumulator with M = 19 wraps at 256 and produces samples of a sine at 19/256 × fclk = 0.0742 fclk.

Worked Example: Tuning Word and Resolution

A DDS with a 32-bit accumulator and a 1 GHz clock has a resolution of 10⁹/2³² = 0.233 Hz. To generate 100 MHz:

Exact tuning word: 100 × 10⁶ × 2³² / 10⁹ = 429,496,729.6.
Rounded tuning word: M = 429,496,730.
Actual output: 429,496,730 × 10⁹/2³² = 100,000,000.093 Hz, an error of 0.093 Hz or about 0.9 parts per billion.

The frequency accuracy of the output is otherwise that of the clock. A clock derived from a TCXO or OCXO carries its fractional error straight through to f_out.

Nyquist limits the output to below f_clk/2. In practice the usable range is often taken as up to about 40 % of f_clk, so that the reconstruction filter has room to separate the wanted output from the first image at f_clk − f_out.

Sinc Rolloff and Images

A DAC holds each sample for a full clock period. This zero-order hold multiplies the spectrum of the ideal impulse samples by

H(f) = sin(πf/f_clk) / (πf/f_clk)

The wanted output therefore drops as its frequency rises: by 0.14 dB at 0.1 f_clk, 0.91 dB at 0.25 f_clk and 2.42 dB at 0.4 f_clk. A DDS swept across its band shows this as a gentle amplitude tilt, which can be corrected digitally with an inverse-sinc filter or by scaling the amplitude word.

DAC output spectrum with sinc envelope, wanted tone at 0.3 fclk and images up to three times the clock — Figure 3: Zero-order-hold sinc envelope with fout = 0.3 fclk. The wanted tone is at −1.3 dB and the first image at 0.7 fclk is at −8.7 dB.

The sampled waveform also contains images at k·f_clk ± f_out for every integer k, weighted by the same sinc envelope, with nulls at multiples of f_clk. In Figure 3, with f_out = 0.3 f_clk, the wanted tone is at −1.3 dB and the first image at 0.7 f_clk is only 7.4 dB below it at −8.7 dB. The reconstruction filter must remove that image to the required spurious level. With a 1 GHz clock and a 300 MHz output, the filter has to pass 300 MHz and reject 700 MHz, which typically calls for an elliptic or high-order Chebyshev response from LC filter design.

Images can also be used deliberately. A band-pass filter placed around f_clk + f_out selects a higher-frequency image, a technique sometimes called super-Nyquist operation. The sinc envelope makes those images weaker, and DAC output structures designed for this mode change the envelope shape, so the available power has to be checked against the DAC’s documented response.

Spurs: Phase Truncation and Amplitude Quantization

The accumulator is typically 32 or 48 bits wide, but a lookup table with 2³² entries would be impractical, so only the top P bits address it. Discarding the lower N − P bits introduces a periodic phase error whose pattern repeats with the accumulator. A periodic error produces discrete spurs rather than a noise floor. The worst-case truncation spur is approximately

spur_max ≈ −6.02 · P dBc

so 12 phase bits give about −72 dBc and 14 bits about −84 dBc. Figure 4 is a simulation with N = 32, P = 10 and a 14-bit amplitude path; the largest spur is −60.1 dBc against a prediction of −60.2 dBc. Whether the spurs appear at all depends on the tuning word: if the lower N − P bits of M are zero, the truncated bits never change and there is no truncation error. Tuning words with many low-order bits set spread the error into many smaller spurs.

Simulated DDS output spectrum with phase truncation spurs reaching about minus 60 dBc — Figure 4: Simulated spectrum with N = 32, P = 10 and 14-bit amplitude. The worst spur is −60.1 dBc, close to the −6.02P estimate.

Amplitude quantization in the lookup table and DAC behaves more like noise when the output and clock frequencies are unrelated. For an ideal D-bit converter the signal-to-quantization-noise ratio over the Nyquist band is

SQNR = 6.02 D + 1.76 dB

A 12-bit DAC gives 74.0 dB. Spread over the 500 MHz Nyquist band of a 1 GHz clock, that is a noise density of −74.0 − 10 log(5 × 10⁸) = −161.0 dBc/Hz. When f_out is a simple fraction of f_clk, the quantization error becomes periodic and concentrates into spurs instead.

DAC Harmonics and Aliasing

In practice the largest spurs usually come from DAC nonlinearity rather than truncation. Harmonics of f_out are generated in the DAC and fold back into the first Nyquist zone. With f_clk = 1 GHz and f_out = 300 MHz:

Harmonic	Unaliased frequency (MHz)	Appears at (MHz)
2nd	600	400
3rd	900	100
4th	1200	200
5th	1500	500

The third harmonic lands at 100 MHz, well inside the passband of any filter that passes 300 MHz, so it cannot be filtered out. The usual remedy is frequency planning: choose f_clk and the output range so that low-order harmonics alias away from the band of interest. Spur levels from DAC nonlinearity depend on the specific converter and are given in its data sheet as SFDR versus output frequency.

Phase Noise of a DDS

A DDS behaves like a fractional frequency divider. The clock’s phase noise is reduced at the output by

L_out(Δf) = L_clk(Δf) − 20 log(f_clk/f_out)

A 1 GHz clock with −140 dBc/Hz at some offset would, in principle, give −160 dBc/Hz at the same offset on a 100 MHz output. The improvement stops at the residual phase noise of the DDS itself, set by jitter in the DAC clocking and its digital logic, and at the quantization noise floor. Low-frequency outputs therefore often hit the residual floor rather than the scaled clock noise.

DDS Compared with a PLL

A PLL synthesizer multiplies a reference up to microwave frequencies using a VCO, with spurs and noise shaped by the loop filter. Its switching time is limited by the loop bandwidth, typically microseconds or longer. A DDS is limited to below half its clock but switches in nanoseconds, has fine resolution without fractional-N techniques, and can switch phase-continuously. The two are often combined: a DDS can serve as a finely tunable reference for a PLL, or a DDS output can be mixed with a fixed PLL to translate it upward. Chirp generation for radar, agile local oscillators and test sources are common uses.

Frequently Asked Questions

How does DDS work?

A phase accumulator adds a tuning word to itself every clock cycle, producing a ramp that wraps around once per output cycle. A lookup table converts the phase to sine amplitude, and a DAC and reconstruction filter turn the samples into an analog sine at M · f_clk/2^N.

What causes spurs in a DDS?

Truncating the accumulator phase to P bits produces spurs up to about −6.02P dBc. Amplitude quantization adds noise or spurs, and DAC nonlinearity produces harmonics that alias into the first Nyquist zone. In practical devices the DAC harmonics are usually the largest.

Why does DDS output amplitude fall with frequency?

The DAC holds each sample for a full clock period, which multiplies the spectrum by sin(πf/f_clk)/(πf/f_clk). The loss is 2.42 dB at 40 % of the clock frequency and grows toward the Nyquist frequency.

What is the maximum output frequency of a DDS?

The theoretical limit is f_clk/2. A common practical limit is about 40 % of f_clk, leaving a transition band for the reconstruction filter. Higher Nyquist zones can be used with a band-pass filter at reduced output level.