Part 4 followed the noise budget through the front end as far as the IF amplifier. An RF ADC, or analog-to-digital converter, ends the analog part of the receive path by turning the amplified signal into samples for digital processing. Its sample rate decides how much spectrum it can see, its noise and resolution decide how much gain must precede it, and those choices feed back into the architecture. This part looks at sampling, ADC noise and gain planning, then brings Parts 1 to 5 together in a receiver case study.
Sampling, Nyquist and Frequency Plans
An ADC sampling at fs represents frequencies only up to fs/2 without ambiguity. Any higher input folds back into that range and is called an alias, so analog filtering has to remove what should not be sampled. For a lowpass signal extending to fmax, the Nyquist criterion requires fs > 2fmax.
That raises an obvious question. How can a 40 MSPS converter, limited to 20 MHz, handle the 98.1 MHz FM signal from Part 2? It cannot sample the RF directly, but the superheterodyne has already moved the signal to 10.7 MHz, comfortably below 20 MHz. The front end exists partly to translate the signal into a range the converter can use.
IF sampling and Nyquist zones
The Nyquist requirement really concerns bandwidth and not the highest frequency. A signal confined to one Nyquist zone, the bands of width fs/2, can be sampled directly from a higher zone, and it will alias cleanly into the first zone. This is IF sampling, or undersampling. With fs = 250 MSPS, a 184 MHz IF sits in zone 2 (125 to 250 MHz) and appears at 250 − 184 = 66 MHz. The second and third harmonics of the IF centre land at 118 MHz and 52 MHz, clear of the 61 to 71 MHz band occupied by a 10 MHz signal. A harmonic spreads with its order, though, so the third harmonic of that signal covers 37 to 67 MHz and overlaps the lower edge of the band at a low level, which the plan has to allow for.
The analog input bandwidth of the ADC must reach the actual 184 MHz, even though the digital result is at 66 MHz. An anti-alias filter then has to remove anything in the other zones that would land on the same place, including noise. A buffer amplifier or balun drives the converter, and it must be flat and linear across the band. Direct RF sampling, covered in Part 13, takes the same idea to multi-gigahertz inputs and removes the mixer completely.
ADC Noise, Resolution and Clock Jitter
An ideal N-bit converter has a quantization SNR of 6.02N + 1.76 dB for a full-scale sine wave, so 12 bits gives 74.0 dB and 14 bits gives 86.0 dB. Real converters fall short of this. Consider a 14-bit, 250 MSPS RF ADC with a measured SNR of 72 dB relative to full scale, and full scale at +4 dBm, about 2 V peak to peak across 200 Ω. The effective number of bits is (72 − 1.76)/6.02 = 11.67.
- Total noise power is +4 − 72 = −68 dBm, spread over 125 MHz.
- Noise density is −68 − 81.0 = −149.0 dBm/Hz.
- In a 9 MHz channel, the ADC noise is −79.4 dBm, a benefit of 11.4 dB over the full Nyquist band. This is processing gain.
Clock jitter sets a further limit, and it gets worse with input frequency: SNRjitter = −20 log10(2πf tj). At 184 MHz with 150 fs of RMS jitter, the limit is 75.2 dB. Combined with 72 dB of converter noise, the total is 70.3 dB, so even this good a clock costs about 1.7 dB. Sampling at a higher IF needs a cleaner clock, which is one reason frequency synthesis matters as much on the converter clock as on the LO.
Spurious-free dynamic range is the other headline specification. SFDR is the gap between a full-scale signal and the largest spur, and with modulated signals it decides whether a strong interferer can create a false in-band response. High-resolution pipeline and modern RF-sampling converters use dither and digital correction to reduce these spurs.
Converter type follows from the bandwidth and resolution. Pipeline and interleaved converters serve wideband IF and RF sampling. Successive-approximation designs cover moderate rates at low power, and sigma-delta converters trade oversampling for resolution in narrower channels, which suits handset baseband paths. Whatever the type, the receiver designer works from the same three numbers: full scale, noise density and spurious level.
How Much Gain Before the RF ADC?
The ADC behaves like one more noisy stage at the end of the cascade. Its noise density can be compared directly with the amplified receiver noise. Take the chain from Part 4 with a small extra allowance for a VGA, giving NF = 4.60 dB. With gain G from antenna to ADC, the analog noise density at the converter is −174.0 + 4.6 + G dBm/Hz.
Too little gain and ADC noise dominates. Too much and strong signals clip. A common rule keeps analog noise about 10 dB above ADC noise, which limits the loss to about 0.4 dB. Here that needs G = 30.4 dB. Figure 1 plots the total noise figure as gain changes.
| Gain to ADC (dB) | Total NF (dB) |
|---|---|
| 20 | 7.82 |
| 25 | 5.90 |
| 30 | 5.05 |
| 34 | 4.79 |
| 40 | 4.65 |
Choosing 34 dB gives 4.79 dB, within 0.19 dB of the analog chain alone. Going to 40 dB would gain only 0.14 dB more and lose 6 dB of headroom. Full scale at the converter maps to +4 − 34 = −30 dBm at the antenna, and that is the price of the high gain.
Case Study: A Modern 10 MHz Receiver
The case study combines the earlier parts into one receiver for a 10 MHz LTE-style downlink at 1842.5 MHz. Figure 2 shows an IF-sampling design. It is simplified, and a handset would use direct conversion instead, but the double-filtered structure keeps each budget visible, and the same reasoning applies to base stations and instruments.
- Frequency plan (Part 2). Low-side LO at 1842.5 − 184 = 1658.5 MHz, with the image at 1474.5 MHz, removed by the duplexer and image filter.
- Linearity (Part 3). Band filters ahead of the LNA reduce out-of-band signals, while in-band blockers must stay within an IIP3 budget like the −8 dBm example.
- Sensitivity (Part 4). Noise of −174.0 + 69.5 + 4.79 dB, less about 1 dB for the required SNR, gives −100.6 dBm before diversity or margin.
- Selectivity. The IF filter gives some adjacent-channel rejection, and digital filters finish the job after the ADC, which is why that converter needs dynamic range to spare.
At that sensitivity, the signal reaches the ADC at −66.6 dBm. That is about 71 dB below full scale, yet it works, because noise and not level decides the result. In-channel analog noise at −65.8 dBm sits 13.6 dB above the ADC noise of −79.4 dBm, so the converter adds little.
What changed from CDMA-era receivers
Earlier receivers of this form were built for narrowband CDMA, with a 1.23 MHz channel. The same equation applies: −174 + 60.9 + 9 dB of NF gives −104.1 dBm of noise, and the widely quoted reference sensitivity was near −104 dBm, at about the noise level. It worked because despreading gave 21.1 dB of processing gain at 9.6 kbit/s. OFDM systems do not get that help. They rely on wider channels, adaptive modulation and multiple antennas, so a 10 MHz channel starts about 9 dB higher in noise, and modern receivers typically hand channel filtering, AGC and I/Q correction to digital hardware. The 5G RF front end shows where that has led.
AGC Before the ADC
Received power varies widely because of distance and fading. Old designs tried to hold a nearly constant level at a low-resolution converter. A 14-bit ADC relaxes that requirement, but an AGC is still needed for overload. Backing off 12 dB for the peaks of an OFDM waveform gives a target of +4 − 12 = −8 dBm at the ADC. At full gain, that is reached with −42 dBm at the antenna, and a −25 dBm signal then needs the gain to drop to 17 dB. The gain range required is only 17 dB, not the full 76 dB dynamic range of Part 4. At −8 dBm the ADC-limited in-channel SNR reaches 71 dB, well above what any modulation needs.
Gain is usually controlled digitally from a received signal strength indication (RSSI) computed after the ADC. An inaccurate RSSI either clips the converter or wastes its range. Digital control has latency, however, and where gain must respond faster than the digital loop an analog loop is used, like the one in Figure 3.
Analog AGC loop design
A coupler samples the VGA output and a detector converts it to a voltage. An op-amp integrator compares that voltage with Vref and drives the VGA control pin. If the output is low, the error ramps the control voltage and raises the gain until the detector output equals Vref. At that point the integrator input current is zero and the loop settles.
Because the integrator forces detector voltage to equal Vref, the steady-state output depends only on the detector and the coupler. The VGA law need not be accurate or temperature stable, so long as it is monotonic. The detector carries the accuracy, and for a fixed setpoint it only has to be stable at one level. A wide-range detector, such as a logarithmic type, lets Vref program the output over a wide span. Strictly, such a loop holds the output level and not the gain, so automatic level control (ALC) is the more exact name.
With a detector slope of 25 mV/dB and a VGA slope of 40 dB/V, the loop gain constant is 1. For an integrator with R = 10 kΩ and C = 10 nF, RC = 100 µs, giving a unity-gain frequency of 1.59 kHz and a 1% settling time of 4.6RC/K = 460 µs. Doubling the VGA slope halves that to 230 µs. If gain varies along the control curve, so does the settling time, which is why a linear-in-dB VGA and a logarithmic detector make a good pair. Too fast a loop also follows the signal envelope and strips off amplitude modulation, so the time constant has to stay well above the modulation period, and extra poles in the detector or VGA can make the loop ring.
Next in the Series
The receive path is now complete, from the antenna to digital samples. Part 6, Transmitter Architectures, reverses the direction and follows bits out to the antenna: superheterodyne and direct-conversion transmitters, EVM budgets, and the polar and envelope-tracking designs built around the power amplifier.