Three developments are needed, however, if the SOP concept is to succeed on a large scale. First, design tools must be developed for the simultaneous design of digital, analog, and optical circuits along with the package. Although tools exist for designing individual digital and analog circuits and for boards themselves, none exist for designing a whole system like ours. Georgia Tech is setting up an industry consortium to focus on developing such tools. And to push SOP to the next generation, we are also arranging several industry consortia on embedded active and passive components, mixed signal testing, nanometer materials and packaging, and thermal material interfaces, among others.
The second development that’s needed would be a change in today’s IC- and system-package manufacturing. Today, semiconductor companies design and fabricate ICs but usually rely on outside companies for their packages. System companies design their systems while counting on packaged ICs from semiconductor companies, system boards from board companies, and the assembly of the entire system by contract manufacturers. But because of the way an SOP is designed and integrated, it must be developed for fabrication at the same time. The manufacturing model will therefore have to change if the SOP method is ever to become mainstream.
The third change needed deals with process technologies. SOP substrates are a hybrid: they need a clean room like those for ICs, thin-film processes along with low-cost, large-area board processes. Accordingly, a number of different manufacturing techniques for SOPs are emerging, including an SOP-like package with thin-film deposition on silicon wafers by Philips; organic boards by Shinko, Ibiden, and Matsushita; and ceramic boards by Murata and TDK.
At Georgia Tech we believe that the market for multifunctional products and the advantages of designing chips and system packages concurrently are so compelling that companies will just have to design and fabricate everything together. And as the SOP concept takes off, design-tool and fabrication houses will turn their attention to developing powerful programs for concurrent design and advanced manufacturing, just as they did in the past decade when the SOC was in its infancy.
Acknowledgment: The author wishes to thank his Georgia Tech team of faculty, engineers, students, and representatives from industry for their contributions included in this article, and both the Georgia Research Alliance and the National Science Foundation—Engineering Research Centers for their funding of SOP technology for more than a decade.
About the Author
RAO R. TUMMALA, an IEEE Fellow, is a member of the National Academy of Engineering and is the Pettit Chair Professor in Microsystems Packaging at the Georgia Institute of Technology, in Atlanta. He is also the founding director of the Microsystems Packaging Research Center, one of the U.S. National Science Foundation’s 22 Engineering Research Centers. Before joining the Georgia Tech faculty, he was an IBM Fellow and director of the company’s Advanced Packaging Technology Laboratory.
To Probe Further
The May 2004 IEEE Transactions on Advanced Packaging was devoted to system-on-package research. See R. Tummala et al., “SOP for Miniaturized Mixed-Signal Computing, Communication, and Consumer Systems of the Next Decade,” pp. 250–267, and R. Tummala, “SOP: What It Is and Why?” pp. 241–249.
Another article describing a high-speed wireless device, by R. Tummala and J. Laskar, “Gigabit wireless: system-on-package technology,” is in Proceedings of the IEEE, Vol. 92, 2004, pp. 376–387.
“Packages Go Vertical,” IEEE Spectrum, August 2001, describes system-in-package technology. “Chips Go Vertical,” Spectrum, March 2004, looks at methods for stacking chips.
