Automation Comes to Analog – IEEE Spectrum

The way Roberts sees it, testing these tiny chips with huge machines just is not the best way. The trend has been to move the testers ever closer to the circuits on the chip. Even with centimeters between the circuits and the test equipment, degradation occurs in the measurement because of signal noise picked up by the electrical leads that connect the tester to the chip under test. To reach the embedded analog blocks, said Roberts, people are modifying the designs to bring signals from the circuits under test to the boundary of the chip. Some designers use drivers, buffers, and test buses on the chip to connect cores, embedded blocks of circuitry on system chips, to the outside world. But for Roberts, that’s not enough.

“The way I see the world,” said Roberts, “test instruments should have the same functionality as the benchtop equipment, but be located on the chip. Miniaturize the measurement instruments and add them as plug-in test cores.”

For that kind of setup, the test cores would need to be small and scale to new process technologies. They should also be synthesizable from a hardware design language, which is where EDA can play a role. Once analog synthesis is mature, said Roberts, test-core blocks will be possible. Essentially, the test core would convert the analog signal to digital, and send that signal to a test pin on the boundary of the chip. With some improvements in the technology used to probe the pins while the chips are fresh from fabrication and still on the wafer, test could be made quite manageable.

Carnegie Mellon’s Rutenbar agrees. With analog synthesis in place, designers will also be able to generate test vectors more easily. But right now, inserting BIST or other test structures is something analog designers avoid. “In analog, it’s so hard just to get the signal path done,” said Rutenbar, “they don’t want to worry about putting test structures in.”

Seeing eye to eye

The relationship between semiconductor makers and the EDA vendors is sometimes a thorny one. Some designers see the tools as immature, requiring them to create time-consuming work-arounds. Others, like National Semiconductor’s Verhoeven, appreciate that EDA vendors allow users to add functionality to their programs with extra scripts. Fortunately, the pure analog chips are coming along just fine with the relatively mature simulation and layout editing tools.

Two things designers and EDA vendors do agree on is that there is always more room for automation and that tools need to be integrated into a more formal top-down design flow. But, said Cadence Design’s Chang, “The analog productivity gap isn’t a show-stopper. The industry adapts pretty well. People work it out.”

­Elizabeth A. Bretz & Linda Geppert, Editors