From tools to methodologies
Tool vendors are pushing more than just tools. Everyone agrees that design methodologies must evolve as well. “Bottom-up analog design is a bottleneck to completing complex mixed-signal [system-on-chip] designs on schedule,” said Michael Jackson, who heads the West Coast R&D group at Avant! Corp., Fremont, Calif. “The most promising area is the transition from bottom-up analog design to top-down design.”
Texas Instruments’ James said she’s already seeing that shift occur. More information for the physical design of analog blocks comes from the chip-level description. “You used to have pure circuit designers,” she said, “and the layout person was pretty separate from the design process.” But now the AMS teams increasingly use the top-down methodologies, which means new job responsibilities for analog engineers.
For EDA to address the needs of AMS designers, EDA vendors must work closely with designers to understand the types of designs in progress, and to help create a coherent methodology that links the piecemeal tools, emphasized Henry Chang, an architect focusing on AMS issues at Cadence Design Systems. New tools will take a while to catch on, said Chang, and will be used only incrementally until designers trust and understand the limitations of the tool for their design types. There is no one-size-fits-all when it comes to EDA tools, so new design practices must fill the gaps.
More help on the way
Tools are still behind the curve in noise analysis and other problems–like harmonic distortion–that come with system-on-chip design. “Crosstalk and noise are critical in high-speed designs,” said National Semiconductor’s Verhoeven. Analog designers must consider noise, drift, temperature coefficients, jitter, nonlinear responses, and transmission line issues. Naturally, such disturbances affect the behavior of the analog circuits. Several companies specialize in developing tools for these aspects of analog design. For instance, Snaketech Inc., in Voiron, France, which was acquired last year by Simplex Solutions Inc., Sunnyvale, Calif., specializes in substrate noise.
Another up-and-coming technology that addresses the demands of analog circuitry is a field-programmable analog array (FPAA) from Anadigm Ltd., Crewe, United Kingdom. The technology is similar to the field-programmable gate array that is a staple of digital systems. The engineer uses software to select circuit elements from among 20 analog function blocks and connects them so as to perform the desired function. The selections are converted into a data stream and downloaded to the FPAA.
Functions that can be implemented using FPAA include offset removal, rectifiers, gain stages, comparators, and first-order filters. The designers can also construct high-order filters, oscillators, pulse-width modulators, and equalizers.
While this technology is very young, and still expensive, it could someday be useful for creating communications products that would work on any standard. For instance, a cell phone with a reprogrammable analog-to-digital converter would search the entire communications band for a signal, then grab the necessary program from memory to make itself into a code-division multiple access (CDMA), time-division multiple access (TDMA), or global system for mobile communications (GSM) phone. Such a phone could be used in Japan, Europe, or the United States without modification.
Testing, testing…
The requirements of testing mixed-signal designs open “a whole new frontier,” according to David Yee, vice chair of the computer-aided design group of Semiconductor Research Corp., Durham, N.C., an organization that helps coordinate collaborative research among universities and industry. In fact, the cost per transistor of manufacturing test will soon exceed the cost of making the transistor–for some larger designs, it already has. In analog test, every transistor on the chip needs to be tested for behavior and performance, unlike digital testing, which only needs to check that the transistors switch. But currently, there are no good solutions to the AMS test problem.
For designs like phase-locked loops (PLLs), which keep certain input signals in sync with one another, current built-in self-test (BIST) structures will work fine. In other circuits, though, such measurements of performance as speed, dynamic range, and resolution cannot be made using BIST.
One issue is that there are sometimes no access pins to the analog block on a system-on-chip design. Yet some connection must link the analog block to the outside world. How to solve this problem is what drives Gordon Roberts, an associate professor in the department of electrical and computer engineering at McGill University in Montreal.
