What you’ll learn:
- Why terabit-scale optical transceivers are needed.
- How to realize terabit/s-class optical transceivers.
- Key SiGe BiCMOS within the transmitter IC.
The growing popularity of data-intensive applications, such as cloud services, video streaming, high-performance computing, and 5G, poses ever-increasing demands on optical communication networks within data centers. Here, the most performant optical links operate at speeds up to 400 Gb/s, using, for example, 4 × 100-Gb/s channels. Data-center operators, however, are forecasting a need for terabit/s-capable optical transceivers within a few years from now.
In parallel to this evolution, co-packaged paradigms are emerging to help optical switches cope with the massive bandwidth density at their input—soon reaching 100 terabits/s. In these co-packaged optics, silicon (Si) photonics transceivers are tightly integrated with the high-speed electronic circuits.
The common research challenge is clear: Simultaneously increasing the capacity of the optical links and fitting the required transceivers in ever smaller footprints. This will require innovations in the electronic and photonic high-speed integrated circuits that make up the transceivers.
Beyond 100-Gbaud Signaling Rates
Contents
One option to realize terabit/s-class optical transceivers is to push the signaling rates well beyond 100 Gbaud—the baud rate being the number of symbols transmitted per second. This may interest you : Packaging Demands For RF And Microwave Devices. On the electronics side, such rates may be beyond the capabilities of even the most advanced CMOS nodes (such as FinFETs), especially in terms of achievable analog bandwidth.
Until now, >100-Gbaud speeds have been mostly the domain of, for instance, indium-phosphide (InP) technologies. Their smaller wafer sizes and reduced capability to integrate more complex functionality makes scaling in such processes challenging. While imec is now pursuing III-V on CMOS processes as a solution in the medium to long term, on the short term, integration of novel circuit architectures in silicon-germanium (SiGe) BiCMOS can be a solution to achieve operation beyond 100 Gbaud.
Scientists from imec-IDLab have now come up with a novel transmitter architecture that has key building blocks fabricated in a mainstream SiGe BiCMOS process. The resulting IC decodes 4x 30-Gbaud PAM-4 (or 4x 60-Gb/s NRZ) streams, and simultaneously multiplexes and equalizes these streams into a 120-Gbaud PAM-4 signal with >80-GHz bandwidth, 1.2-V p-p voltage swing, and 2200-mW power consumption. Since the 4-level pulse amplitude PAM-4 modulation format involves two bits per symbol (denoted as 00, 01, 10, and 11), this is the equivalent of a 240-Gb/s (single lane) transmitter.
Key SiGe BiCMOS Components in an Innovative Architecture
Within the transmitter IC, a multiplexer (MUX) combines multiple low-speed input signals (coming from, say, a CPU or GPU within the data center) into a single full-rate data stream. This stream is subsequently equalized to compensate for any bandwidth losses in the modulator and the channel. This may interest you : Samsung suffers more than 300 bln-won loss due to monthlong Texas chip shutdown. The high-speed equalized signal is then used as an input signal for the driver that subsequently feeds the optical modulator.
In traditional transmitter architectures, equalization is performed in the digital domain by using a digital signal processor (DSP) fabricated in advanced CMOS nodes. The equalized signal is then converted into an analog signal, feeding the driver. When high-voltage swings are required, this driver is nowadays fabricated in III/V technology.
IDLabs’ transmitter IC architecture implements an analog-signal-processing variant of the DSP filter, i.e., a 7-tap mixed-signal fast-forward equalizer (FFE) with finite-impulse-response (FIR) filter (Fig. 1). Moreover, all key components, i.e., the integrated MUX, FFE, and driver are fabricated in mainstream 55-nm SiGe BiCMOS technology.
%{[ data-embed-type=”image” data-embed-id=”60897ac32f5c132a008b48ea” data-embed-element=”span” data-embed-size=”640w” data-embed-alt=”1. On the left is a block diagram and on the right is a die micrography, both showing the 4:1 PAM-4 serializer chip with mixed-signal FFE, as presented at 2021 CICC.” data-embed-src=”https://img.electronicdesign.com/files/base/ebm/electronicdesign/image/2021/04/Fig_1___Block_diagram_and_die_micrograph.60897ac360fb1.png?auto=format&fit=max&w=1440″ data-embed-caption=”1. On the left is a block diagram and on the right is a die micrography, both showing the 4:1 PAM-4 serializer chip with mixed-signal FFE, as presented at 2021 CICC.” ]}%
A 120-Gbaud PAM-4 Prototype
In a prototype transmitter IC, four 30-Gbaud PAM-4 input signals are processed to obtain the two components of the PAM-4 signal, i.e., the most- and least-significant-bit (MSB and LSB) signals. Read also : Mouser Electronics Adds Over 70 New Manufacturers in 2020 to Its Industry-Leading Line Card. The 4xMSB and 4xLSB signals are separately multiplexed and filtered by the 7-tap FFEs.
The filtered signals are combined in the output stage to obtain a full-rate 120-Gbaud PAM-4 signal, feeding the driver. The transmitter chip is flip-chipped on a high-speed PCB to allow for electrical evaluation (Fig. 2). The work shows a doubling of the operating rate compared to FinFET solutions and closely matches the speed and power obtained in InP-based solutions.
%{[ data-embed-type=”image” data-embed-id=”60897ae5c0152fa3148b47e7″ data-embed-element=”span” data-embed-size=”640w” data-embed-alt=”2. Shown is a PAM-4 eye diagram at 120 Gbaud on a flip-chipped sample with the FFE optimized to reach 500 mV p-p output, compensating around 8 dB of loss at 60 GHz.” data-embed-src=”https://img.electronicdesign.com/files/base/ebm/electronicdesign/image/2021/04/Fig_2___120Gbaud_image.60897ae4de484.png?auto=format&fit=max&w=1440″ data-embed-caption=”2. Shown is a PAM-4 eye diagram at 120 Gbaud on a flip-chipped sample with the FFE optimized to reach 500 mV p-p output, compensating around 8 dB of loss at 60 GHz.” ]}%
Future Work
The >100-Gbaud chips enable progression toward a new generation of optical transceivers. They would transmit these signals in either multiple fibers or at multiple wavelengths to achieve the bit rates required for the terabit era. Apart from the building blocks described earlier, the team also is working on >100-Gbaud transimpedance amplifiers and modulator drivers, high-sampling-rate ADCs, and 100-Gsample/s analog time interleavers.
These building blocks also will be crucial for developing novel coherent transceiver concepts, which exploit the phase and polarization of the optical field to further increase the bit rate. The coherent transceivers target optical communication applications where low cost and low energy are critical objectives.
More details can be found in the 2021CICC paper “A 4-to-1 240 Gb/s PAM-4 MUX with a 7-tap Mixed-Signal FFE in 55nm BiCMOS,” authored by M. Verplaetse et al. To receive the paper, fill in this contact form.
