The next step, as more powerful analog-to-digital and digital-to analog converters (ADCs and DACs) become commercially available, is to achieve programmability at higher frequencies, first I-F and later RF.
Right away, the transceiver needs only half as much hardware as the conventional configuration. Instead of multiple transmit and receive chains, programmable radios have just one of each, which can be programmed to handle whatever radio standard is used by the subscriber’s network–and even others that do not yet exist!
The higher-frequency functions, like filters and mixers, are hard to make programmable in silicon, which is by far the most common and least expensive chip material. The speeds required to implement them digitally exceed silicon’s reach. The I-F section of a GSM cellphone runs at a few hundred megahertz, no problem for any modern silicon IC process. But to implement that same function digitally in the same processor that runs the rest of the cellphone’s functions means executing around 100 billion instructions per second, a much more difficult feat, and one that may require silicon-germanium chips. To put the number in perspective, the single-purpose silicon chips in present-day cellphones execute roughly 10-100 million instructions per second.
Quartet of key technologies
The component technologies that form the backbone of SDR systems–and set their performance limits–are ADCs, digital signal processors, filters, and RF amplifiers.
The ADC is the most critical element of an SDR since its speed determines how close to the antenna the analog-to-digital conversion can be done. Defining ADC performance is always difficult because it involves specifying both analog and digital parameters. In essence, three main areas must be characterized: speed (number of samples per second), resolution (how many bits each sample is coded into), and linearity (how accurately the digital output codes are related to the analog input values).
For SDR purposes, the situation is as follows: The fastest ADCs in commercial use today–the kind found in the fastest digital oscilloscopes–can acquire roughly 10 billion samples per second. They cost too much and consume too much power to succeed in the cellphone application.
An ADC priced low enough and with enough resolution for use in cellphones can acquire about 100 million samples per second. That’s high enough to digitize the I-F section of the transceiver–sampling the entire I-F cellular band and extracting individual channels in the digital domain–but it is nowhere near up to the job of digitizing the RF portion of the radio.
A straightforward approach to implementing a software-defined radio is to use a direct-conversion architecture in which analog circuitry downconverts the RF signal directly to baseband, skipping the I-F stage completely. The signal is then digitized by an ADC after which the desired channel is selected using selection filters implemented in a DSP.
While it is elegant in concept, direct conversion faces some formidable challenges in practice, according to Zoran Zvonar, systems development manager at Analog Devices Inc. (Wilmington, Mass.). Among the barriers to IC realizations of direct-conversion radios, there are difficulties in reducing dc voltage offsets to the point at which compensation techniques can eliminate them completely so they do not degrade overall system performance.
The DSP is the fundamental building block of SDR. It can implement at least two radio interfaces at the same time, as is necessary when switching over from one radio standard to another. This sort of thing will become more common in the future, when cellphones need to link to other personal electronic devices over Bluetooth connections. In such cases, DSPs may have to run several parallel radio interfaces, much as some computers run multiple applications simultaneously. In general, functions assigned to a DSP include compressing and decompressing speech, modulation and demodulation, and filtering.
