Improving reliability and performance of RF ICs with advanced EDA technology
IntroductionContents1 Introduction2 RF IC verification challenges3 Design topology checking4 Rule checks5 RF/Analog layout checking6 STI stress and WPE effects7 RF/Analog layout fill insertion8 Summary9 Author With recent advancements in process technology, such as the development of high resistivity substrates, the integration of passive devices on-die, and the integration of bipolar junction transistors (BJTs) and complementary […]
Improving reliability and performance of RF ICs with advanced EDA technology Read More »