By Louis Fan Fei, Garmin International

The three major building blocks in a modern, fully-integrated transceiver are a transmitter (TX), a receiver (RX), and a synthesizer. A synthesizer design is quite different from the TX or the RX. Both a TX and a RX have a higher analog content. The synthesizer design has significantly higher digital content. It challenges the designer’s analog and digital skills.

In some instances, what appears to be an analog function is actually implemented with a digital block. For example, a frequency divider and a phase/frequency detector (PFD) are routinely implemented with the digital building blocks. In other instances, what appears to be a digital block needs a carefully analog design, such as a charge pump (CP). In the voltage controlled oscillator (VCO) design, both analog and digital building circuits are needed. The required knowledge of mixed-signal circuits makes a synthesizer a challenging design to work on.

A synthesizer is used to generate a very stable carrier signal for the TX and the RX. It is used to switch a transceiver to a different channel. The important requirements are: integrated in-band phase noise, spur level, channel switching speed, frequency step resolution, local oscillator pulling, power consumption, and low power supply rail.

The two popular synthesizer architectures are an integer-N and a fractional-N phase-locked loop (PLL). If an integer-N PLL can meet the requirement, it should be used because of a relatively simpler design. But in most cases, especially the multi-band, multi-mode transceivers used in cellular applications, a fine frequency resolution and a fast switching time are needed. In those cases, a fraction-N will have to be used. There are many good references on the synthesizer system and the digital control block design. This paper focuses on the detailed analog/RF circuit portion. The CP, PFDs, frequency dividers, VCOs are discussed below. All the pure digital signal processing (DSP), such as delta-sigma (Δ Σ), are left out because it is a topic all by itself.

1. CMOS charge pump

Charge Pump
A charge pump (CP) is used in the synthesizer to source or sink current from an external loop filter. The basic idea is to add a switch in both the current source and current sink paths. The switch can be added at the gate, source, or drain. To reduce the effect of the charge sharing, clock feed-through, and charge injection, switching at the source is the best choice because the switch is relatively isolated from the output. Switch at source topology is shown in Figure 1a. Icp is the reference current for both the current sink and the current source. For the current sink path, Icp is mirrored into the M6&M5 path through the modified stacked current mirror (M1, M2, M5, M6). The advantage of this current mirror is the low supply voltage requirement compared with the standard stacked current mirror. M15 is the source switch for the current sink. M13 is the dummy FET to ensure M1 and M5 have the same DC source voltage. For the current source path, Icp is first mirrored by modified stacked current mirror (M1, M2, M3 and M4). Then it is mirrored again by the PMOS current mirror (M7, M8, M9, M10). M11 is the switch for the current source.

To reduce the mismatch problem and to increase the speed of the CP, a current steering CP (Figure 1b) is often used. The switches are implemented with a current steering pair (M1&M2, M3&M4). Icp is mirrored to the current steering pair via the modified stacked current mirror. To source the current, UP is logic H and /UP is logic low. Icp goes through the path of M1, then it reaches output via another current mirror (M5&M6). To sink the current, DOWN control pair is activated. Because the current is steered instead of charging/discharging, Figure 1b will be faster than Figure 1a. But it will burn more power since the current path is not really shut off when it is not used.

Phase/Frequency Detector
The UP/DOWN control signals used in the CP are generated by the phase/frequency detector (PFD). The two D-type flip-flop (DFF) implementation has been a work horse for a long time. Its block diagram and the circuit implementation are shown in Figure 2a. The upper and lower DFFs generate UP and DOWN signals, respectively. When f1 arrives first at the upper DFF, the UP signal is generated to turn on the current source. When f2 arrives at the lower DFF, its output is logic H. When both UP and DOWN are logic H, NAND gate resets both DFFs to output logic L. Thus the phase difference between the two signals are detected and used to turn on either the current sink or current source of the CP.

2a. CMOS PFD

To improve the speed, simplicity is key. By using the faster and simpler logic, like the true single phase clock (TSPC), the DFF can be implemented with just a few transistors instead of a few gates. One popular implementation is shown in Figure 2b. Transistors from M1 to M9 forms the upper latch, while the transistors from M11 to M19 form the bottom latch. The two latches are identical.

2b. PFD with TSPC logic

On the upper latch, the FETs from M1 to M6 are basically a modified version of the standard doubled n-C²MOS latch with precharge technique. The theory of operation is as follows. Assume f1 and f2 are both low at the start. Node A is precharged to logic high. As f1 transition from low to high and f2 stays low, M5 is turned on and M5 turns on the inverter formed by M4 and M6. Node B is pulled low. M7 and M8 is an inverter to give the UP signal. M9 is added to fix one special problem in this architecture. Because the top and bottom latches can’t be perfectly matched in delay, there will be narrow pulse for both UP and DOWN output even with no input phase difference. With M9, node A is discharged to GND. As f1 rises from low to high, node B is pulled up to logic H. Thus UP output will be pulled down. The bottom latch works on the same theory.

The reset circuitry is essentially built into this architecture. There is no feedback reset logic circuitry needed in the traditional PFD in Figure 2a. Because of this, the reset delay is short. The PFD with TSPC implementation will have a much higher operating frequency. (Low GHz operating frequencies have been reported by many researchers.)

Frequency Divider
Typically a divide-by-2 block is designed first. Then, multiple basic blocks are cascaded together to get a higher divider ratio. For the high-speed portion of the synthesizer, such as the prescaler that immediately follows the VCO output, source couple logic (SCL) is a good choice. The block diagram and the circuit implementation are illustrated in figure 3a.

3a. Frequency divider with ECL

As shown in the block diagram, the basic building block is the DFF (D type flip-flop). The two DFFs work in a master-slave fashion. In the first half of the clock cycle, the master DFF is on and the input data is clocked in. The slave DFF is off. In the second half of the clock cycle, the master DFF’s output is transferred to the slave DFF. The output toggles at the next clock edge. Thus, the output frequency will be half of the input frequency. A frequency divider is essentially a digital building block.

The circuit implementation is also shown in figure 3a. M1 to M8 form the master DFF. M9 to M16 are the second DFF. Since the two DFFs are identical, we can focus on just one DFF. M1 and M2 are the buffer for the input RF signal. M5 and M6 are the latch element. M2 and M3 are the logic element. M7 and M8 are the diode tied load. When RF input is high, M4 to M6 are shut off. The input at the M2&M3 pair is loaded into the DFF. When RF input is low, the already loaded inputs are latched into the M5&M6 pair. Because of the current steering technique used, the ECL is very fast. Thus, it is suitable for RF applications.

As the VCO output frequency is divided down, the operating frequency gets much lower after the prescaler. A simple and cheaper TSPC frequency divider can be used. The most basic form is shown in 3b.

3b. TSPC Frequency Divider

Transistors Q1 to Q6 form the master latches. Transistors Q7 to Q12 form the slave latches. Q13 and Q14 are simply the inverter to complete the feedback path needed in the toggle latch. The master latch is sometimes called double NC²MOS because two NFETs are needed in the pull-down network (PDN). Similarly, the slave latch is sometimes refereed as the double PC²MOS because two PFETs are needed in the pull-up network (PUN). When the clock is high, the master latch is activated while the slave latch is off. (The opposite is true when the clock is low.)

VCO
The CMOS VCO is based on the negative resistance theory. The NMOS-only version is presented in Fig 4a. By cross coupling M1 and M2, a positive feedback is created in the circuit. Looking into the gate of M1 and M2, a negative resistance can be expected. The operating frequency is set by the resonant tank. L1 and L2 provide the inductance part. The frequency can be tuned coarsely by the capacitance banks and fine tuned with the varactor caps. In Fig 4a, two bit 4 states capacitance banks are used. More banks can be added if a larger process variation is expected. By turning on/off M7 and M8, more/less total capacitance can be expected in the resonator tank. The varactor is implemented with FETs M5 and M6 by tying the source and the drain. M3 and M4 are the output buffers.

4a. NMOS only VCO

Complementary CMOS VCO is presented in figure 4b. The key change is to add a cross coupled PMOS pair. By adding a PMOS pair, two more active elements are added to contribute the negative resistance while the bias current remains the same. So it is more power efficient.

4b. Complementary CMOS VCO

Since the DSP portion of the synthesizer is already in standard cell form, the development time for a fully integrated CMOS synthesizer can be greatly reduced. The circuit topologies presented here are generic and they are widely used. They can be considered as a good starting point for your next design.

References

1. Behzad Razavi, "RF Microelectronics," Prentice-Hall, 1998.

2. Randall L. Geiger, Phillip E. Allen, Noel R. Strader, "VLSI design techniques for analog and digital circuits", McGraw-Hill, 1990.

3. Behzad Razavi, "Design of Analog CMOS Integrated Circuits", McGraw-Hill, 2001.

4. Thomas H. Lee, "The Design of CMOS Radio-Frequency Integrated Circuits", Cambridge University Press, 2004.

5. M. H. Perrott, High speed communication circuit and systems, MIT OCW 2003.

6. Allen Podell, RFIC Design and Applications, Besser Associates short course.

7. James Young, RF CMOS Design, Besser Associates short course.

8. Ulrich L. Rohde, David P. Newkirk, "RF/Microwave Circuit Design for Wireless Applications", John Wiley & Sons, Inc., 2000.

9. Jan Crols, Michiel Steyaert, "CMOS Wireless Transceiver Design," Kluwer Academic Publishers, 2003.

10. Louis Fan Fei, "CMOS Oscillator Design Considerations," Microwave Journal, April, 2007.

11. Louis Fan Fei, "Enhance CMOS Charge pumps and phase-frequency detectors," Microwaves and RF, Sep. 2007.

12. Louis Fan Fei, "Frequency divider design strategies," RF Design, March, 2005.

About the Author
Louis Fan Fei is currently an RF engineer at Garmin International where he has designed GPS receivers since 2003. He worked on WLAN and wireless local loop circuits at Lucent/Agere System from 1998 to 2003. He also worked on microwave instrument circuits for HP/Agilent in Colorado Springs in the summer of 1997. He has more than 17 technical publications. He received his BEE and MSEE from Georgia Tech in 1996 and 1998, respectively.

By Louis Fan Fei, Garmin International

To meet the demands for the multi-band, multi-mode wireless standards in the current market, a highly integrated wireless receiver (RX) is desired. CMOS technology has become the technology of choice for the integrated receiver design. CMOS’s raw performance is not as good as SiGe or GaAs. But most of the baseband (BB) ICs are implemented with CMOS. Thus, it gives the advantage to CMOS in applications where a single chip that combines RF and BB IC is desired. The cost advantages of established CMOS manufacturing processes are also a factor to consider.

A traditional heterodyne RX converts the RF signal to the intermediate frequency (IF) stage. At every stage, various filters, such as surface acoustic wave (SAW) ones, are used to filter out the image signal, to select the channel, and to reduce the effects of any interfering signals. It is hard to achieve a fully-integrated receiver because of the required external components. Direct-conversion RX has become the dominant RX architecture. The well-known problems with a direct conversion RX like DC offset, high input second order intercept point (IIP2), and 1/f noise can be resolved with various correction loops in the BB and careful RFIC designs.

The major RX performance parameters are RX sensitivity, RX selectivity, dynamic range, IIP2, IIP3, and phase noise. The RX sensitivity is mostly set by the front end low noise amplifier (LNA) and the demodulator (DEMOD). The RX selectivity is determined by the on-chip low pass filter (LPF)’s rejection performance. Dynamic range, IIP2, and IIP3 are the measures of how robust a RX is with the presence of in-band and out-of-band interferences. Phase noise has a major impact on the signal modulation and demodulation as phase-shift key modulation is commonly used. This article thus will focus the major building blocks in the RX that influence receiver performance.

1. CMOS LNA.

A LNA’s noise figure (NF) and gain performance are the most dominant factors in the RX’s sensitivity. It is difficult to achieve the best performance of one parameter without sacrificing the other. The gain and NF compromise is a classical tradeoff. A single ended and a differential version of the popular LNA designs are shown in Figure 1.

The Miller multiply effect increases the parasitic capacitance at the gate of the LNA. A Cascode topology reduces this effect by stacking a common gate (CG) stage on a common source (CS) gain stage. The input and output port are better isolated to reduce the parasitic capacitance between the gate and the drain. In Figure 1a, M1is the CS stage while M2 is the CG stage. L1 is the degenerated feedback element to bring the input NF circle and the gain circle closer. Thus a compromise between the NF and the gain can be reached. L3 is the input matching element. C1 is the input DC block. The LNA is biased in a current mirror configuration with M3, I1, and R1. In a highly integrated IC circuit, the common mode noise is a major problem.

A differential circuit is often used to combat this problem. The differential LNA is presented in Figure 1b. It can be considered as two single-ended LNAs with the tail bias current. The tail current out of the M7 is important to reduce the common mode noise. Without it, there will not be enough common mode degenerated resistance to reduce the common mode noise. The bias current is set by the current mirror made from M6 and M7. It in turn sets the Vgs of M1 and M2. The drain voltage of M7 is set by the current mirror biasing at the gate of the M1 and M2.

2. CMOS DEMOD

A demodulator is used to convert an RF signal to the baseband. Since most modern wireless devices require both I and Q channels, two double balanced mixers (DBM) are needed in the DEMOD. The implementation is illustrated in Figure 2. M1 to M6 is the DBM for I channel. M11 to M16 is the DBM for Q channel. Since the same DBM is used for both I and Q channel, only one DBM is discussed in details. The incoming RF signal is amplified first by the gain stage such as M1 and M2. M3 to M6 are the switching FETs. It fundamentally serves the purpose of a multiply operation. In half the cycle, M3 and M6 are on. Local oscillator (LO) and RF are essentially multiplied in phase. In the other half the cycle, M4 and M5 are turned on to reverse the polarity of the output signal. The output loads are implemented with resistor R1 to R4. The degenerated feedback inductor L1 to L4 helps the IIP3 performance. The biasing is done with thediode connected FETs.

3a. Variable transconductance AGC

3b. Variable biasing AGC

There are many automatic gain control (AGC) topologies to choose from. The variable transconductance and the variable biasing AGC are the most popular for high-frequency operation. The variable transconductance circuit is shown in Figure 3a. It is based on the principle that the transconductance of the FET changes as the FET goes from a saturation mode to a triode mode. Thus, the gain is varied. M1 to M4 can be considered as the typical differential cascode gain stage. The difference is that Vcont is applied at the gates of M3 and M4. As Vcont decreases, the drain voltage at M1 and M2 drops. Eventually M1 and M2 enters the triode region as Vcont is lowered to below Vgs1+Vs1-Vt. M7 to M10 are the current source type load. Thus a common mode feedback (CMFB) is needed to make sure the current source matches with the current sink I1. The common mode voltage is sampled at the drain of M3 and M4 with M5 and M6. M5 and M6 can be considered as two large value resistors. They have the same value.

The sampled voltage is fed to a comparator (M11 to M14). The reference is fed to one input M14 while the sampled common mode is fed to the other input M13. The error voltage is used to control the bias current out of the current source M8 and M9. (M8 and M9 are the current bleeding path.) The closed feedback loop ensures correct bias current follows with the desired reference voltage.

A variable current AGC is based on the idea that the tranconductance of a FET changes with the bias current. By varying the bias current in the FET, the AGC can be accomplished. Such an implementation is presented in Figure 3b. M1 and M2 are the input gain buffer. M4 and M5 are the current bleeding path. If Vcont is larger than the Vref, more bias current flows through M3 and M6. In this mode, a high gain is expected. When the Vcon is reduced, more bias current flows through M4 and M5, the gain is thus reduced. M7 and M8 are the output emitter follower buffers to reduce output impedance. R1 is the degenerated resistor to improve the linearity of the AGC.

4a. NMOS only VCO.

4b. Complementary CMOS VCO

The CMOS VCO is based on the negative resistance theory. The Negative Metal Oxide Semiconductor (NMOS)-only version is presented in Fig 4a. By cross coupling M1 and M2, a positive feedback is created in the circuit. Looking into the gate of M1 and M2, a negative resistance can be expected. The operating frequency is set by the resonant tank. L1 and L2 provide the inductance part. The frequency can be tuned coarsely by the capacitance banks and fine tuned with the varactor caps. In Fig 4a, two bit 4 states capacitance banks are used. More banks can be added if a larger process variation is expected. By turning on/off M7 and M8, more/less total capacitance can be expected in the resonator tank. The varactor is implemented with FETs M5 and M6 by tying the source and the drain. M3 and M4 are the output buffers. Complementary CMOS VCO is presented in figure 4b. The key change is to add a cross-coupled Positive-Channel Metal Oxide Semiconductor (PMOS) pair. By adding a PMOS pair, two more elements are added to contribute the negative resistance while the bias current remains the same. So it is more power efficient.

The topologies presented are generic enough to be used in most wireless standards. They can be considered as a good starting point for your next CMOS RX design.

References

1. Behzad Razavi, "RF Microelectronics", Prentice-Hall, 1998.

2. Randall L. Geiger, Phillip E. Allen, Noel R. Strader, "VLSI design techniques for analog and digital circuits", McGraw-Hill, 1990.

3. Behzad Razavi, "Design of Analog CMOS Integrated Circuits", McGraw-Hill, 2001.

4. Thomas H. Lee, "The Design of CMOS Radio-Frequency Integrated Circuits", Cambridge University Press, 2004.

5. Allen Podell, RFIC Design and Applications, Besser Associates short course.

6. James Young, RF CMOS Design, Besser Associates short course.

7. John W. Rogers, "Radio Frequency Integrated Circuit Design", Artech House, 2003.

8. Ulrich L. Rohde, David P. Newkirk, "RF/Microwave Circuit Design for Wireless Applications", John Wiley & Sons, Inc., 2000.

9. Jan Crols, Michiel Steyaert, "CMOS Wireless Transceiver Design," Kluwer Academic Publishers, 2003.

10. Louis Fan Fei, "Subharmonic Mixer IC designs and enhancement techniques", Microwave Journal, Sep. 2005.

11. Louis Fan Fei, "CMOS Oscillator Design Considerations", Microwave Journal, April, 2007.

12. Louis Fan Fei, "CMOS AGC Design Strategies", TBD.

About the Author
Louis Fan Fei is currently an RF engineer at Garmin International where he designs GPS receivers since 2003. He worked on WLAN and wireless local loop circuits at Lucent/Agere System from 1998 to 2003. He also worked on microwave instrument circuit for HP/Agilent in Colorado Springs in the summer of 1997. He has more than 17 technical publications. He received his BEE and MSEE from Georgia Tech in 1996 and 1998, respectively.

By Yiqun Lin, Silicon Laboratories

A critical limitation in taping out high-performance mixed-signal ICs is the characterization of complex analog/RF blocks such as phase locked loops (PLLs) and analog-to-digital converters (ADCs). As we strive to extend our leadership in the semiconductor business, we are always looking for ways to accelerate our analog/RF verification flow without increasing the risk of silicon that does not meet specifications. We have three key requirements for analog/RF simulators: accuracy, performance and capacity. This article describes the application of Analog FastSPICE^TM (AFS) from Berkeley Design Automation (BDA) to the pre-tapeout characterization of a nanometer-scale CMOS PLL, sigma-delta ADC and an automatic gain control (AGC) circuit. These production circuits are representative of our most complex analog/RF blocks. In each case, we compared the results of our "golden" traditional SPICE simulator with those of AFS. Despite our initial skepticism, AFS met or exceeded BDA’s claims on all counts " identical waveforms, 5 -10x higher performance and sufficiently higher capacity to handle our most complex applications. We now rely on AFS to verify our most difficult complex blocks and even to run our full-circuit simulations.

Analog/RF Design at Silicon Laboratories
Silicon Laboratories offers a diverse portfolio of high-performance, analog-intensive, mixed-signal ICs that provide significant advantages in performance, size and power consumption. These patented solutions serve a broad set of markets and applications including consumer, communications, computing, industrial and automotive. These designs are typically analog- and/or RF-intensive, using a variety of complex blocks that include sigma-delta ADCs, PLLs (frac-N and integer-N), DLLs, dc-dc converters, PHYs, CDRs, frequency synthesizers, transmit chains and receive chains. These types of design blocks represent some of the biggest challenges in our design flow is verification and characterization.

Characterizing Complex Analog/RF Blocks
Over the years, we established a proven and robust transistor-level SPICE-based flow that works well for small analog and RF blocks. Our flow minimizes post-tapeout issues, and it is a requirement for our designers. Our block-level verification needs are not unique: we require pre-layout and post-layout circuit simulation, validate process corners, run noise characterization and perform RF analysis on periodic circuits. We depend on the "golden" SPICE accuracy with tight tolerances to validate functionality and performance. Without this accuracy, we would face a significant risk of taping out an analog or RF block that is not functional or does not meet specifications.

One of our key challenges was to scale our SPICE-based analog/RF verification flow as the complexity of our analog and RF blocks increased. Our design complexity is growing at a very rapid pace, driven by both the integration of analog functionality into SoCs and the growth in new functionality requirements in the markets we serve. The SPICE flow we use for small blocks was insufficient for our complex analog/RF circuits. Simulating these blocks required days to weeks, and in many cases, would not converge at all.

We also need to verify our analog/RF ICs at the top-level. This helps us ensure that we have correct full-circuit connectivity, functionality and performance specifications. Finally, we want to extend our methodology to support a mixed-signal flow with fast gate-level and behavioral Verilog-based simulations for the digital portion and SPICE-accurate transistor-level simulation for the complex analog/RF blocks. Again, traditional SPICE runtime and convergence issues limited us in pursuing this flow.

Digital FastSPICE Tools Fall Short
One of the alternatives we tried for our complex analog/RF block verification is FastSPICE tools, originally developed for digital and memory circuits. These tools are faster than traditional SPICE but at the expense of accuracy. They use simplified device models, partition the circuit into independent sub-circuits, require block-level simulator tuning and rely on hierarchical modeling. We found that these simplifications sacrifice accuracy to a degree that they were impractical for our leading-edge analog/RF circuits. The problems we encountered included having to tune the simulator extensively block-by-block, inability to get DC convergence and results that missed the targets we measured in silicon.

Our Experience with Analog FastSPICE
We had a breakthrough when we started using Analog FastSPICE. AFS produces results that are identical to our "golden" SPICE tool down to the SPICE noise floor, at least 5x faster and with much higher capacity. AFS finishes week-long SPICE simulations in only days and day-long SPICE runs in only a few hours. This performance and capacity allows us to simulate large circuits and verify our circuits at the top-level as well.

It was important that AFS did not cut corners and had the same capabilities as our traditional SPICE tool. A true test for the overall functionality of the tool is observing its behavior on highly non-linear circuits, since circuit simulators typically have difficulty handling non-linear behavior. One of the best ways to do this is to perform a transient simulation of a real-time clock (RTC) circuit to test RTC current consumption with complex digital control sequence. Figure 1 shows the results of AFS simulation of a RTC circuit. The RTC current measurement shows many sharp current pulses over long simulation time. The result is extremely accurate and predicts a leakage current that matches silicon.

1. Analog FastSPICE Transient Results for RTC.
Click here for a larger version

AFS plugs directly in our existing flow using the same netlists, models and testbenches. The output format is the same as our SPICE simulator, so we can process it with our existing post-processing scripts.

The first circuit is an automatic gain control block (AGC) with bandgap and bias circuitry. It also contained several Verilog-A models. We ran a transient simulation to verify the ramp-up to the DC operating point. Our traditional SPICE simulator took 13.5 hours to complete. The digital fastSPICE simulator struggled and could not successfully run this circuit. AFS finished the simulation in 22 minutes with identical waveforms for a 36x speed-up versus SPICE.

The second circuit is a third-order sigma-delta ADC with 9-bit resolution. It has a 1 MHz bandwidth, a 16 MHz sampling frequency and a 1V 200 KHz input. We had two versions of this circuit: a pre-layout version with 14,882 elements (11,265 MOS) and a post-layout version with 63,642 elements (14,832 MOS). We ran transient simulation the pre-layout version for 63 us and then post-processed the data to calculate the signal-to-noise ratio (SNR). The traditional SPICE simulator, the digital fastSPICE simulator with very tight settings, and AFS predicted similar SNR results. AFS complete the run 27 times faster than traditional SPICE and more than four times faster than digital fastSPICE. Figure 2 shows the AFS results for the sigma-delta ADC noise profile. The top red curve is the ideal response and the bottom blue curve is the result with parasitic extraction. Given the AFS performance advantage, it was the only tool we used on post-layout circuit.

The first circuit is an automatic gain control block (AGC) with bandgap and bias circuitry. It also contained several Verilog-A models. We ran a transient simulation to verify the ramp-up to the DC operating point. Our traditional SPICE simulator took 13.5 hours to complete. The digital fastSPICE simulator struggled and could not successfully run this circuit. AFS finished the simulation in 22 minutes with identical waveforms for a 36x speed-up versus SPICE.

The second circuit is a third-order sigma-delta ADC with 9-bit resolution. It has a 1 MHz bandwidth, a 16 MHz sampling frequency and a 1V 200 KHz input. We had two versions of this circuit: a pre-layout version with 14,882 elements (11,265 MOS) and a post-layout version with 63,642 elements (14,832 MOS). We ran transient simulation the pre-layout version for 63 us and then post-processed the data to calculate the signal-to-noise ratio (SNR). The traditional SPICE simulator, the digital fastSPICE simulator with very tight settings, and AFS predicted similar SNR results. AFS complete the run 27 times faster than traditional SPICE and more than four times faster than digital fastSPICE. Figure 2 shows the AFS results for the sigma-delta ADC noise profile. The top red curve is the ideal response and the bottom blue curve is the result with parasitic extraction. Given the AFS performance advantage, it was the only tool we used on post-layout circuit.

2. Analog FastSPICE Noise Profile for Sigma-Delta ADC.
Click here for a larger version

The third example is a PLL with 3 GHz VCO frequency, 24 MHz reference frequency, and 150 KHz bandwidth. We ran a 20us transient simulation with traditional SPICE to measure the locking process. For traditional SPICE, we had to break the run into two stages: the first stage used liberal accuracy in order to quickly get near the locking state, and the second stage used the result from the first stage as initial conditions and switched back to moderate for more accurate locking results. The whole process in traditional SPICE took up to three weeks. Digital fastSPICE required tuning block-level accuracy settings and then took 40 hours. AFS completed a 25 us run in 20 hours. AFS was 25 times faster than traditional SPICE. Compared to digital fastSPICE, AFS did not require any tuning, ran two times faster and produced SPICE-accurate results.

We use our simulation results to make decisions that have a huge impact on our company. It is extremely inefficient to respin designs because complex analog/RF blocks are not meeting functional or performance specifications. The performance improvements of the digital fastSPICE tools relative to the traditional SPICE simulator come with a significant cost. The accuracy of the digital fastSPICE tool is never guaranteed to be the same as that of traditional SPICE. Traditional SPICE always runs with tight accuracy as controlled by the simulation relative tolerance (reltol), which affects size of time-step and controls the allowed difference between iterations before converging at a timepoint and moving on to the next. SPICE defaults reltol to 1e-3 (0.1 percent) with typical values set from 1e-2 to 1e-6. We compared AFS simulation results against those of traditional SPICE simulation with different reltol settings. Only after we are sure that a tool delivers the required accuracy do we start to look at the performance and capacity capabilities.

We found that Analog FastSPICE has the required accuracy and in several cases is more than 20 times faster than traditional SPICE. Now, what is truly incredible is that in our circuits, AFS was also be two to four times faster than the digital fastSPICE tools without using techniques that can compromise accuracy. Essentially, we get the accuracy of traditional SPICE with better performance than digital fastSPICE.

Summary and Future Work
Analog FastSPICE is the best simulator we found in terms of accuracy, speed, capacity and ease-of-use. It delivers true SPICE accuracy with higher performance than the existing digital fastSPICE tools for our applications. AFS is ideal for large transistor-level simulation " including analog behavioral models " and does not require block-level tuning. In our experience, its performance is five to 30 times that of other SPICE simulators and can converge on circuits much larger than traditional SPICE tools can handle.

For future work, we are looking at using Analog FastSPICE noise analysis, including random device noise analysis of non-periodic blocks such as sigma-delta ADCs and fractional-N PLLs. We are also looking forward to using Analog FastSPICE Verilog-D co-simulation in the future. This capability would enable us to extend our methodology to tackle much larger mixed-signal circuits, with Verilog simulation for digital blocks and AFS transistor-level simulation for the complex analog/RF blocks.

About the Author
Yiqun Lin is Staff CAD Engineer at Silicon Laboratories Inc. He has more than 15 years combined EDA and design experience. He has engineering degrees from Florida Institute of Technology and Shanghai Jiao Tong University with 3 IEEE publications and holds 2 US patents.

Traditionally, multiple IC chips are needed to build transmitters (Tx) used in wireless communications. The difficulty with a full Tx integration is that each Tx building block uses different technology. A power-detection circuit will exploit the Schottky diode, while the modulator IC is integrated with BiCMOS or SiGe. Likewise, the digital control loop is implemented in CMOS. Now that direct-conversion Tx uses digital control loop for nonlinearity corrections, CMOS

Although, CMOS technology itself can’t compete with GaAs, HBT, SiGe or BiCMOS technologies, a CMOS Tx can be integrated with a powerful DSP. Thus, by using DSP many CMOS deficiencies can be alleviated. For example, by using a predistortion technique for a PA along with the DSP, the nonlinearity problem can be dramatically improved. For an efficiency-related problem, the techniques such as polar loop, Doherty, dynamic bias or linear amplification with nonlinear components (LINC) can improve the performance. The major building blocks in a highly integrated Tx are a PA, a modulator (MOD), a power detector (PD), an automatic gain control circuit (AGC) and the voltage-controlled oscillator (VCO). Typical implementation of each of these blocks will be discussed.

The CMOS PA has gradually replaced the HBT or GaAs FET in the low to medium (up to 20 dBm) power applications like Bluetooth and WLAN at 2.4 GHz to 2.5 GHz and 5.1 GHz to 5.9 GHz. For a CMOS IC, the common-mode noise is an issue. The differential configuration is the answer. The output power can be combined at the final stage with a balun or left it as a differential interface if the post PA SAW is balanced or a dipole type antenna is used.

A PA design’s emphasis is on the output power, power gain, linearity and efficiency. The design starts at the output port where the output power contours of the device are characterized. Once the output termination is determined, the matching circuit is designed the same way as the other RF building block’s matching circuits. A two-stage common-source FET with the RC feedback is shown in Figure 1(a). M1 and M2 are the driver stages. M3 and M4 are the output power stages. RC feedback from the drain to the gate stabilizes the transistors at the high frequency. The feedback also widens the bandwidth of the PA. M5 and M6 and M7 and M8 are the active resistive dividers to bias the driver stage and the power stage, respectively. The cascode PA design is popular as well. One such implementation is shown in Figure 1(b). Topology wise, it is similar to a cascode LNA. The advantage of the cascode configuration is to reduce the Miller multiply effect. Miller effect comes into play because of the parasitic capacitance between a FET’s gate and its drain. In a common-source (CS) amplifier, it will be a problem. By inserting a common gate (CG) stage in the cascode configuration, the output and input are isolated. The input capacitance is also reduced. The additional advantage is more gain for the same amount of bias current since the bias current is reused. M1 through M4 are the driver stage while M5 to M8 complete the power stage. An integrated balun is used in this design since most widely used antennas in wireless devices are single ended.

A PD is used to monitor the PA’s output power level. The PD’s output dc voltage is fed back to the baseband for processing. A PD can be implemented in many ways. It could be as simple as a diode or a FET circuit. Or it could be as complicated as a circuit with hundreds of transistors. The level of complexity depends on the requirements for a PD. The important design parameters for a PD are dynamic range, linear-in-dB linearity, power consumption, ease of integration and its operating frequency.

A PD with one simple FET is presented in Figure 2. The basic idea is to use the square term of the active device. M1 is the active device. M1 is biased at the borderline between triode and saturation region. It means the Vbias or Vgs is set to be Vds + Vt. The drain of the FET is close to zero. So if Vgs is slightly higher than Vt will bias M1 at the border line between the triode and saturation region. The standard equation for the drain current of a FET transistor in the saturation region is as follow:

K is the device parameter that includes the physical dimensions of the device, electron mobility and oxide capacitance. Since Vgs = Vds + Vt, then Vds can be expressed as Vds = Vgs-Vt. Equation 1 can be further simplified to:

With equation 2, the square law relationship between the input RF signal and output-rectified current is established. This is why the RF input is applied at the drain, not M1′s gate. The rectified output current goes through load resistor R3 to establish the output voltage. R2 and C3 are the output filter. A FET can be configured in a common-source configuration as in an amplifier. It has the square law characteristics as seen in equation 1. But the Vt term will create an undesired dc offset term.

raditionally, multiple IC chips are needed to build transmitters (Tx) used in wireless communications. The difficulty with a full Tx integration is that each Tx building block uses different technology. A power-detection circuit will exploit the Schottky diode, while the modulator IC is integrated with BiCMOS or SiGe. Likewise, the digital control loop is implemented in CMOS. Now that direct-conversion Tx uses digital control loop for nonlinearity corrections, CMOS

To get a high dynamic range (>60 dB), cascading the basic PD will extend the detection range. A popular and a high-performance implementation is the log-amp type. The generic multistages topology is illustrated in Figure 3(a). The basic building blocks are the limiter amplifiers, the rectifiers and a summer. The limiter amplifier has a rectifier at both the input and the output. The limiter’s job is to provide gain and clip the output signal at a certain designed output level. The limiter amplifier nearest to the output port will clip first. Then stage by stage, the rest of the limiter will clip. A higher number of the gain stages will result in better linearity or linear-in-dB performance. The reason is each rectifier has a good linear power detection range. But the linear range is limited. By breaking up the total dynamic range into multiple numbers of linear regions, a piece-wise linear-in-dB approximation can be achieved. The limiter can be as simple as a differential amplifier with resistive load as shown in Figure 3(c). The rectifier is essentially a current rectifier as shown in Figure 3(b). The basic building block is an asymmetric differential amplifier pair. When Vin is small, most of the tail current flows through bigger FETs like M2 and M4. As Vin increases, the tail current is gradually steered into M1 and M3. So the output current linearly decreases as Vin is increased. Thus, a full-wave current rectifier is achieved.

The MOD is used to upconvert a baseband (BB) signal to the RF frequency. Since most modern wireless devices require both I and Q channels, two double-balanced mixers (DBM) are needed in a MOD. The implementation is illustrated in Figure 4. M1 to M6 is the DBM for I channel. M11 to M16 is the DBM for Q channel. Since the same DBM is used for both I and Q channel, only one DBM is discussed in detail. The incoming BB signal is amplified first by the gain stage such as M1 and M2. M3 to M6 are the switching FETs. It fundamentally serves the purpose of a multiply operation. In half the cycle, M3 and M6 are on. Local oscillator (LO) and BB signals are essentially multiplied in phase. In the other half of the cycle, M4 and M5 are turned on to reverse the polarity of the output signal. The output loads are implemented with resistors R1 and R2. The summer network can be simply done by routing both the I and the Q output current to the load resistor. The input stage can be configured in CG stage to avoid the voltage to current nonlinearity in the CS input stage.

There are many AGC topologies to choose from. The variable transconductance and the variable biasing AGC are the most popular for the high-frequency operation. The variable transconductance circuit is shown in Figure 5(a). It is based on the principle the transconductance of the FET changes as the FET goes from a saturation mode to a triode mode. Thus, the gain is varied. M1 to M4 can be considered as the typical differential cascode gain stage. The difference is that Vcont is applied at the gates of M3 and M4. As the Vcont decreases, the drain voltage at M1 and M2 drops. Eventually, M1 and M2 enters the triode region as Vcont is lowered to below Vgs1+Vs1-Vt. M7 to M10 are the current source type load. Thus, a common-mode feedback (CMFB) is needed to make sure the current source matches with the current sink I1. The common-mode voltage is sampled at the drain of M3 and M4 with M5 and M6. M5 and M6 can be considered as two large value resistors. They have the same value. The sampled voltage is fed to a comparator (M11 to M14). The reference is fed to one input M14 while the sampled common mode is fed to the other input M13. The error voltage is used to control the bias current out of the current source M8 and M9. M8 and M9 are the current bleeding path. The closed feedback loop ensures correct bias current follows with the desired reference voltage.

A variable current AGC is based on the idea that the transconductance of a FET changes with the bias current. By varying the bias current in the FET, the AGC can be accomplished. Such an implementation is presented in Figure 5(b). M1 and M2 are the input gain buffer. M4 and M5 are the current bleeding path. If Vcont is larger than the Vref, more bias current flows through M3 and M6. In this mode, a high gain is expected. When the Vcont is reduced, more bias current flows through M4 and M5, the gain is thus reduced. M7 and M8 are the output emitter follower buffers to reduce output impedance. R1 is the degenerated resistor to improve the linearity of the AGC.

The CMOS VCO is based on the negative resistance theory. The NMOS-only version is presented in Figure 6(a). By cross coupling M1 and M2, a positive feedback is created in the circuit. Looking into the gate of M1 and M2, a negative resistance can be expected. The operating frequency is set by the resonant tank. L1 and L2 provide the inductance part. The frequency can be tuned coarsely by the capacitance bank and fine tuned with the varactor capacitance. In Figure 6(a), two bit four states capacitance banks are used. More banks can be added if a larger process variation is expected. By turning on/off M7 and M8, more/less total capacitance can be expected in the resonator tank. The varactor is implemented with FETs M5 and M6 by tying the source and the drain. M3 and M4 are the output buffers. Complementary CMOS VCO is presented in Figure 6(b). The key change is to add a cross-coupled PMOS pair. By adding a PMOS pair, two more elements are added to contribute the negative resistance while the bias current remains the same. So it is more power efficient.

Each major building block in a highly integrated Tx is discussed in this article. The circuits are generic enough to be adopted in most wireless applications. This article offers a good starting point for your next Tx RFIC design.

1.  

   Randall L. Geiger, Phillip E. Allen, Noel R. Strader, “VLSI Design Techniques for Analog and Digital Circuits,” McGraw-Hill, 1990.

2.  

   Behzad Razavi, “Design of Analog CMOS Integrated Circuits,” McGraw-Hill, 2001.

3.  

   Thomas H. Lee, “The Design of CMOS Radio-Frequency Integrated Circuits,” Cambridge University Press, 2004.

4.  

   John P. Uyemura, “Introduction to VLSI Circuits and Systems,” John Wiley & Sons, 2002.

5.  

   S. C. Cripps, “RF Power Amplifier for Wireless Communication,” Boston, MA: Artech House, 1999.

6.  

   John W. Rogers, “Radio Frequency Integrated Circuit Design,” Artech House, 2003.

7.  

   Louis Fan Fei, “CMOS Power Amplifier Design Strategies,” Microwave & RF, November 2007.

Louis Fan Fei is currently an RF engineer at Garmin International, Olathe, KS, where he has been designing GPS receivers since 2003. He worked on WLAN and wireless local loop circuits at Lucent/Agere System from 1998 to 2003. He received his BEE and MSEE from Georgia Tech in 1996 and 1998, respectively.