Fractional N

Fractional N

F & Wireless

Delta-Sigma Fractional-N Synthesizers Enable Low-Cost, Low-Power, Frequency-Agile Software Radio

By Qinghong Du, Electronics Design Engineer, Conexant Systems, Inc.

PLL basics

A phase locked loop (PLL) is a negative feedback loop in which the phase of a generated signal is forced to follow that of a reference signal. A basic modern PLL comprises a reference source, a phase frequency detector, a charge pump (CP), a loop filter, and a voltage controlled oscillator (VCO). The output of the VCO is phase compared with the reference at the phase frequency detector (PFD). The polarity of the measured phase difference is used to turn on the pump-up or pump-down current source in the charge pump. As a result, some charge will be transferred to or taken away from the integrating capacitor in the loop filter. The amount of charge is proportional to the magnitude of the phase difference. This in turn results in an adjustment in the tuning voltage of the VCO so that its phase is retarded or advanced. The loop is designed such that the phase error will be corrected. The function of the PFD also ensures that it will switch on the right current source, i.e., pump-up current or pump-down current, to speed up or slow down the VCO in case of a frequency difference between the two incoming signals to the PFD. When the loop reaches lock condition, the frequency of the generated signal is also equal to that of the reference.

Fundamentals of integer-N frequency synthesizer

When a frequency divider is placed between the VCO and the PFD, the PLL becomes a frequency synthesizer where the output is an integer multiple of the reference. A frequency divider is, in essence, a state machine clocked by the VCO. A rising edge occurs at the divider output every N VCO cycles. Here, N is a predetermined number and is referred to as the division ratio. Since the loop forces the frequency of the divider output to track that of the reference, the VCO is N times as fast as the reference. That is,

fvco = N * fref (1)

where fvco is the output frequency of the VCO and fref is the reference frequency. The above equation indicates that a frequency synthesizer can be viewed as a frequency multiplier with its input and output frequency related by Equation (1).

If the frequency division ratio is made programmable, an integer N frequency synthesizer is formed, as is shown in Figure 1. A programmable divider is a loadable digital counter. Its output completes a cycle every N VCO cycles, much like a simple frequency divider. Since the division ratio is programmable, the output frequency, fvco, can be changed by programming N to a new value. Note that the synthesizable frequencies can only be integer multiples of the input reference frequency, hence the name of integer-N synthesizer. As a result, the minimum channel spacing, or frequency step size, is equal to fref. As we will see in later sections, this is a primary constraint of integer N synthesizers.

Figure 1 A basic integer-N synthesizer architecture

Fractional-N frequency synthesis

The term “fractional-N” describes a family of synthesizers that allow the minimum frequency step to be a fraction of the reference frequency. In other words, the synthesized frequency can be a non-integer multiple of the reference, i.e.,

fvco = fref(N+ k/M) (2)

where k and M are integer numbers. M is a measure of the fractionality that a fractional-N synthesizer can provide. It is usually referred to as “fractional modulus” or “fractional denominator”. k can assume any number between 0 and M. The non-integer number N+K/M is often written as N.F, where the dot denotes a decimal point and N and F represent the integer and fractional parts of the number, respectively.

Over the years, a number of methods have been proposed to realize fractional-N frequency synthesis that are based on the basic concepts of traditional integer N synthesis [1-5]. Among these methods, three techniques are best known in the industry. They are fractional divider based, current injection based and Delta Sigma Modulator based fractional-N. We will discuss the three methods in the following subsections. The last two methods are based on the concept of division ratio averaging and will be dealt with in one subsection.

Fractional divider based fractional-N

This technique evolves from the fundamental principles of integer-N synthesis. The only difference is that the frequency divider is replaced with a fractional divider. A fractional frequency divider is no longer a simple digital counter. The period of the divider output, Tdo, is given by,

Tdo = (N+0.F) Tvco (3)

where 0.F denotes a fractional number and Tvco is the period of the VCO. Here we need to emphasize that the period of a fractional divider output is ideally not time varying once N and 0.F are set. In other words, a rising edge occurs at the output each and every N and 0.F VCO cycles. Figure 2 is a timing diagram illustrating the operation of a fractional divider where N.F is set to be 2.25.

Figure 2 Timing diagram of a fractional N frequency divider

As in the case of an integer N synthesizer, Tdo is forced to follow the reference period. We therefore have,

Tref = (N + 0.F)Tvco (4)

or,

fvco = (N + 0.F) fref (5)

where Tref is the reference period.

We now move to a brief description of a simple circuit realization of a fractional frequency divider. The block diagram is depicted in Figure3.

Figure 3 An example of fractional N divider implementation

As is clear from this figure, the divider comprises a dual modulus divider (DMD), a delay locked loop (DLL), a multiplexer (MUX) and a digital phase accumulator (DPA). Note, however, that a fractional divider does not have to be based on a DLL [6]. The DLL shown in this figure consists of a set of cascaded, tunable, delay elements, a PD, a CP and a D-type flip flop. The negative nature of the feedback in the DLL ensures that the total delay through the delay line is one VCO cycle. Since the delay elements are, ideally, identical, a VCO period is broken up into Nd equal “packets” of phase, where Nd is the number of delay elements in the delay line.

Figure 4 Design of a simple digital phase accumulator

A simple DPA is made up of an adder and a register, as is shown in Figure 4. The register is clocked by the reference. The input to the DPA is an m-bit word. The contents of the register are used to control the MUX. On every reference rising edge, the contents will be incremented by the value of the input, x, which is represented by an m bits word. The output of the DPA, i.e., the carry-out of the adder, is a 1-bit quantization of the input. The number of bits in the accumulator, i.e., m, is related to the number of discrete “packets” of phase by,

Nd = 2^m (6)

the output of the DPA controls the DMD. When “carry-out” is high, the DMD divides by N+1 as opposed to N when “carry-out” is low. As we will see in the following example, the fractional division ratio, N + 0.F, for a DPA input of x is equal to N + x/2m. Suppose the DPA has 3 bits and, therefore, the delay line has 8 elements. Each phase “packet” corresponds to 1/8 of a VCO cycle. Also, assume that the input is equal to 2, which corresponds to a 0.F of 2/8. When no carry-out occurs, the DMD divides by N. Its output, however, is not immediately presented to the PFD of the PLL. Rather, it will be delayed by a number of phase “packets” controlled or selected by the MUX. This number is equal to the content of the DPA, which is incremented by 2 every reference cycle. This means that the output is phase shifted by a progressively increasing number of phase “packets”, i.e., 0, 2, 4, 6, 8, each reference cycle. As a result, the period of the DMD output is increased by 2/8 of a VCO cycle. Therefore, the effective division ratio becomes N+0.25, which is what it should be. When the DPA content reaches 8, the content of DPA will be reset and the output of the DMD will not be delayed by the delay line. However, this coincides with a carry-out, which forces the DMD to divide by N+1. This is equivalent to the DMD dividing by N and its output being delayed by 8 phase “packets”, i.e., one VCO cycle.

The design of the fractional divider dictates the fractional modulus or fractional denominator to be Nd, the number of delay elements. Since all the elements in the delay line operate at the VCO speed, the added power consumption can be significant, especially when the VCO frequency and/or fractionality is high. Another drawback of this method is that the edges of the fractional divider output may be “contaminated” or jittery as a result of jitter on the outputs of the delay elements. Jitter is present due to mismatch and phase error due to the phase error correcting action of the DLL. The edge contamination may result in a significant increase in the PD noise floor, as we will discuss later.

“Averaging” fractional-N

Another way of achieving fractional-N synthesis is through division ratio averaging. The idea is that an integer frequency divider, as opposed to a fractional one, is used but the division ratio is dynamically switched between two or more values. Effectively, the divider divides by a non-integer number. This number is determined by the values among which the division ratio is changed and the probability of each division ratio used. For example, if the divider divides by 100 half of the time and by 101 the other half of the time, the average division ratio is 100.5. In general, the non-integer division ratio is given by,

N.F= N1P1+N2P2+… NjPj (7)

where N.F denotes the average division ratio, Ni and Pi are the integer division ratio and the probabilities associated with them, respectively. Again, as the average divider output frequency is equal to fref, when the loop is in lock, we have,

fvco = N.F * fref (8)

One way of switching the division ratio dynamically is through the use of a simple modulus controller. A modulus controller can be a simple DPA. The output of the DPA is used to control the division ratio of a DMD. The divider divides by N+1 when there is a carry-out and by N otherwise. In this case, the fractional part of the average division ratio is equal to the input to the DPA. This statement can be proven as follows. First, the average value of the DPA output is equal to its input, which is the way a DPA works. This average is also equal to the probability of the DPA carryout being an “1”. Knowing this probability, p, the average division ratio can be readily calculated as,

N.F = N + p (9)

where p is related to the input of the DPA by,

p = x/2^m (10)

Note that the input of the DPA, x, is represented by an m-bit word.

It can be shown that a DPA, as depicted in Figure 4, is actually a first order delta-sigma modulator. Like any delta sigma modulator, the output of a DPA exhibits quantization errors. In the following subsections, we will discuss how the quantization error results in quantization phase error and how to deal with it. As will be clear later, there are two ways of dealing with this error: cancellation by current injection or delta sigma noise shaping. These two techniques lead to two different types of averaging fractional-N synthesis, namely, the current injection based fractional-N and delta sigma fractional-N.

Quantization phase error

The following discussion on quantization phase error is based on a DPA controlled dual modulus divider. To facilitate the definition, we need to imagine an ideal fractional frequency divider that divides by N.F. Here, by “ideal” we mean that the period of the imaginary divider output is always N.F VCO cycles precisely. It adds no noise or jitter to its output.

The existence of quantization error in the DPA output is due to the fact that the output is a “guess” at the input and is never equal to the desired value. This is simply because the output is either 0 or 1 while the input is between 0 and 1 (excluding 0 and 1). Accordingly, the instantaneous division ratio of the DMD is never equal to the average division ratio by which the imaginary divider divides. This, in turn, gives rise to phase difference between the actual instantaneous DMD output and the imaginary divider output. If the latter is viewed as a “reference”, then the former exhibits phase error with respect to the latter. This phase error is defined as quantization phase error or quantization phase noise. It is also referred to as quantization noise for simplicity. Here, there are two points worth mentioning. First, the imaginary divider output will be phase locked to the reference. The phase difference between the two signals will be such that there is no error correction signal at the output of the charge pump. Secondly, the waveform of the actual DMD output can be viewed as the imaginary divider output with its phase being modified by the quantization phase error. With this understanding, the DPA controlled DMD can be modeled as an ideal fractional divider plus a quantization noise source, as is shown in a Figure 5.

Figure 5 A linearized phase-domain model of a PLL with quantization noise source

The above figure can be used to derive the transfer function for the quantization phase error in the s domain, i.e., the transfer function from this phase error source to the VCO output. It is given as,

(11)

where phi-q(s) denotes the input quantization noise and phi-q,o(s) the output, F(s) is the impedance of the loop filter, Kcp and Kvco are the charge pump gain and VCO sensitivity, respectively. Note that other noise sources are not shown in Figure 5. These include the phase noise on the reference, noise due to the CP/PD, VCO noise and random noise due to the divider. The quantization phase error causes phase error at the PFD. The waveform of the phase error sensed by the PFD is the quantization phase error with, possibly, some dc offset. The phase error at the PFD gives rise to a current signal at the charge pump output. The current waveform is a scaled version of the phase error with the scaling factor being the charge pump gain. The current signal is converted to a voltage signal by the loop filter. The latter will modulate the instantaneous frequency of the VCO. If the quantization phase error waveform exhibits some periodicity and if the magnitude of the waveform is large, it will show up in the voltage signal as well. As a consequence, the VCO will be modulated periodically, which gives rise to spurs in the VCO spectrum at the offset frequency corresponding to the periodicity of the current waveform and its harmonics. In the following discussion, we will show that the quantization phase error waveform does exhibit some periodicity.

Let us first derive the relation between the DPA output and the quantization phase error. Suppose that at the present reference cycle the DMD divides by N. This means that the present DMD cycle is shorter than one period of the imaginary divider by (N.F-N) Tvco. That is, the phase error, in radians, changes by (N.F-N) Tvco2Pi/N.F Tvco = (N.F-N)2Pi/N.F. Here, a convention is assumed: when the imaginary divider output leads the actual DMD output, the sign of the phase error is positive. If the DMD divides by N+1, the DMD cycle is longer than one imaginary cycle by (N+1-N.F) Tvco. This corresponds to a change in the phase error by -(N+1-N.F)2Pi/N.F = (N.F-N-1)2Pi/N.F. Thus, regardless of the DPA output, the phase error changes by (N.F-Ni)2Pi/N.F where Ni is the DPA output for the present reference cycle. Therefore, the instantaneous quantization phase error, Phi, is related to Ni by

(12)

this equation indicates that the quantization phase error is a time integrated and scaled version of the DPA output. It can be seen that the output waveform of a DPA exhibits a periodicity of fref0.F. This is because, on average, every 1/0.F reference cycles a carry-out occurs, i.e., the DPA outputs an 1. According to the above equation, the waveform of quantization phase error will exhibit the same periodicity as in the DPA output waveform. Figure 6 shows a quantization phase error waveform together with its corresponding DPA output waveform, where 0.F is equal to 0.25.

Figure 6 A DMD output waveform and its corresponding quantization phase error

A couple of observations on the figure are worth making. The DPA output stays low for 3 consecutive cycles every 4 reference cycles. During these three cycles, the actual DMD output lags the imaginary divider output, causing the quantization phase error to grow continuously. On the subsequent 4th cycle, the phase error returns to its minimum level. After which it starts to ramp up again. As a result, the quantization phase error is a repetitive ramp waveform.

Following the previous discussion on the effect of the periodicity in the quantization phase error waveform, we know that this causes spurs in the VCO spectrum at offset frequencies of plus-minus fref0.F, plus-minus 2fref0.F, plus-minus 3fref0.F…. Since these spurs occur at multiples of fref0.F with 0.F being the fractional part of the average division ratio, they are called “fractional spurs.”

Current injection based fractional compensation

The fractional spurs in the above-mentioned averaging fractional-N synthesis are a serious problem. The magnitude of the periodic waveform of the resulting quantization phase error waveform is large compared to random jitters on the DMD output or the reference, yielding fractional spurs typically only 20 to 30 dB below the carrier [2]. As a consequence, various methods of suppressing these spurs have been devised [1,7]

Returning to the derivation of Equation (12), we notice that the quantization phase error changes by a well-defined amount every reference cycle. If we can somehow inject a current pulse train with the same width but opposite sign to the integrating capacitor in the loop filter, then the quantization phase error can be ideally cancelled. This is called “fractional compensation”.

Usually, mismatches exist between the amplitude and width of the compensation current and those of the charge pump, and therefore cancellation of the quantization phase error is imperfect. As a result, fractional spurs can still be quite large.

There is an important point to note when comparing current injection based fractional-N with fractional division as discussed in an earlier section. Fractional frequency division is commonly viewed as a method of “fractional compensation”. In this view, the fractional divider is broken into two parts; a DPA controlled DMD and a DLL based phase error cancellation circuitry. The quantization phase error introduced by the DPA controlled DMD is cancelled before it is presented to the PFD. This way, no current injection is needed ideally.

Delta Sigma noise shaping

In order to gain some understanding of delta-sigma noise shaping, we need to move from the time domain to the frequency domain. A quantization phase error waveform has a corresponding frequency domain spectrum. Let us first examine the spectrum of the quantization phase error produced by a DPA controlled DMD. Following the previous discussion about the waveform of this phase error, we know that the spectrum has large-amplitude components at multiples of 0.Ffref. In other words, most of the energy appears at or around these frequencies. The idea of using delta-sigma noise shaping is to first “spread” the energy in these tones evenly across some frequency range and then pushing the energy in the low frequencies to high frequencies. This can be accomplished by using a high-order delta sigma modulator to control the dual (or multiple) modulus divider. For simplicity, the adjective “high order” will be dropped. In other words, the term “delta-sigma ” used in this paper is intended to mean high order, typically 4th order.

The spread of energy in the large tones results from the fact that the periodicity in a simple DPA output is destroyed when moving to delta-sigma modulator. Figure 7 shows a waveform of quantization phase error where the input to the modulator is equal to 0.25, the clock frequency is at 25 MHz and the integer part of the division ratio is 100. Its corresponding quantization noise spectrum is shown in Figure 8. As is clear from the two figures, the periodicity seen in Figure 6 is reduced. Correspondingly, the quantization phase noise spectrum has no large tones in its spectrum. Also, the energy in the quantization noise is moved to high frequencies due to noise shaping.

Figure 7 Quantization phase error for a 4th order delta sigma modulator

Figure 8 Quantization phase noise spectrum corresponding to the waveform in Figure 7

Lastly, we want to point out that the quantization phase noise for an nth order delta-sigma modulator only exhibits an (n-1) order of noise shaping characteristic. This is due to the fact that the quantization phase error is a time-integrated version of the modulator output (see Equation 12). The quantization noise spectrum shown in Figure 8 is for a 4th order delta-sigma modulator. It, however, only has a roll-off of 60dB per decade.

Quantization noise attenuation and loop filter design consideration

As was mentioned previously, a delta-sigma modulator controlled DMD or multiple modulus divider (MMD) can be modeled as an ideal fractional frequency divider plus a quantization noise source (see Figure 5). In other words, the delta-sigma modulator and DMD or MMD, as a whole, inject “quantization noise” into the PLL just as other blocks introduce random noise.

The high-frequency quantization noise such as that shown in Figure 8 can result in unacceptably high phase noise in the synthesizer spectrum if the loop filter is not well designed. According to Equation (11), the transfer function for quantization noise exhibits a low-pass characteristic, just like the one for phase noise on the reference. Therefore, quantization noise outside the loop bandwidth can be attenuated by the low-pass filtering function of the loop. Inside the loop bandwidth, the quantization noise is low enough not to affect the overall phase noise due to noise shaping.

The key to loop filter design for delta-sigma fractional-N is to ensure that quantization noise at high frequencies is sufficiently attenuated. In the case where a wide loop bandwidth is required, one or two poles need to be added to a typical one-zero, two-pole loop filter. The two added poles should not be too close to the existing, lower-frequency pole as to not affect loop stability.

Traditional Integer N Synthesizer Trade-off’s

1. Performance parameters of frequency synthesizers

Performance-wise, important parameters of a synthesizer include phase noise, frequency step size or frequency resolution, tuning speed or channel switching speed, spur size and operating frequency range.

Other important parameters include current consumption, power supply voltage, cost, package size, pin count, etc.

In the following subsections, we will discuss in detail the major trade-off’s in integer N frequency synthesis. A good understanding of these trade-off’s is expected to be helpful in appreciating the benefits of fractional-N synthesizers.

2. Trade-off’s between step size and tuning speed

As was mentioned previously, in integer N synthesizers the step size is tied to the reference frequency. A small step size requires a low fref. On the other hand, the loop bandwidth is limited by the reference frequency. The loop bandwidth should be sufficiently lower than fref in order to keep the reference feedthrough low. As a rule of thumb, the loop bandwidth should be at least 10 times lower than the reference frequency to avoid the sampling effect of the PFD. Thus, the smaller the step size, the narrower the loop bandwidth. However, loop bandwidth is the primary factor in determining tuning speed. Generally speaking, the wider the loop bandwidth, the faster the channel switching speed. Therefore, small step size conflicts with fast loop response unless high reference feedthrough spurs can be tolerated.

3. Trade-off’s between step size and phase noise

Phase noise at a given offset frequency is determined by the in-band phase noise floor and the loop bandwidth. At a fixed offset frequency, phase noise can be lowered by narrowing loop bandwidth, i.e., at the cost of slower channel switching speed. The in-band phase noise floor is mainly determined by two factors: the input-referred PD/CP noise and the frequency division ratio, N. More specifically, it is given by,

Phase noise floor = input-referred PD/CP noise floor + 20logN (13)

The input-referred PD/CP noise is the PD/CP noise when back referred to the input of the phase detector. This way, the PD/CP noise sources are “moved” to the input of the PD and are treated as a phase noise on the reference, while the PD and CP themselves are left noise free. Around the phase locked loop, each and every building block contributes to the in-band phase noise. In theory, it is a sum of (a) multiplied reference phase noise, (b) multiplied input-referred PD/CP phase noise, (c) multiplied quantization noise, (d) suppressed VCO noise, and (e) phase noise contribution from the divider. The meaning of the first three terms will be clear shortly. In modern frequency synthesizers, the contribution from PD/CP usually dominates that from other noise sources inside the loop bandwidth. Consequently, only the PD/CP noise contribution appears in Equation (13). It is well known that inside the loop bandwidth the phase noise on the reference, in radians, is multiplied by N when it appears in the spectrum of the output. The reason for this is that the phase noise on the reference, in time, is forced to be equal to the phase noise on the VCO output in time, while the reference period is N times as long as the VCO period. The law of multiplication by N holds for input referred PD/CP noise and quantization noise as well. This law simply states that for a fixed VCO frequency, the phase noise floor goes down by 6 dB for every doubling of reference frequency. However, in the real world, this is often not the case. The reason is that the input-referred PD/CP noise floor can also be dependent on fref. In fact, it goes up with increasing fref. As a result, one may not get a 6 dB decrease in phase noise floor for every doubling fref. In some synthesizers, the improvement is only about 3 dB.

The above discussion shows that the phase noise floor conflicts with the step size. This conflict can be mitigated, somewhat, by choosing a narrow loop bandwidth. However, the loop bandwidth cannot be infinitely small, otherwise the loop will be susceptible to mechanical vibration and other disturbances such as variation on power supply and VCO load pulling. Secondly, narrow loop bandwidth means slow channel switching speed.

4. Trade-off between step size and reference feedthrough spurs

There are two reasons for this trade-off. The first reason has to do with tuning speed or loop bandwidth. For a given loop bandwidth, the higher the reference frequency, the lower the feedthrough spurs. The second reason has to do with various leakages through the charge pump (as a result of finite output impedance), capacitors in the loop filter, and the VCO capacitor. At low reference frequencies, a typical charge pump outputs short alternating pulses of current, with long periods in between in which the charge pump is tri-stated. The various leakages cause a modulating signal in the VCO tuning line. The key point here is that the amplitude of the modulation signal increases with decreasing fref. Therefore, the lower the reference frequency, the higher the reference feedthrough spurs, if leakage is the dominating cause of the spurs. It is believed that at low reference frequencies, e.g., around or less than 30 kHz, leakage is the dominant cause of spurs [8].

Summary of the integer N synthesizer trade-off’s

The trade-off’s can be summarized by use of the following chart. Performance parameters are placed in circles while “intermediate” parameters are inside rectangles.

Figure 9 A performance parameter summary

Before proceeding with an explanation of the chart, we want to clear up a possible confusion between performance parameter phase noise and intermediate parameter phase noise floor. The latter, as was defined previously, is exclusively determined by the input-referred PD/CP noise floor and the frequency division ratio N. Phase noise, or, more specifically, phase noise at given offset frequencies, can be affected by the loop band width in addition to phase noise floor.

Each of the four performance parameters is assigned an arrow with a unique shape and a given direction. The directions of the arrows indicate the desired performance. Up-pointing arrows represent “high”, “large”, “fast” and “wide” while down-pointing arrows symbolize “low”, “small”, “slow” and “narrow”. For example, small reference feed-through spurs are desirable, and therefore a down-pointing arrow is assigned to it.

Each performance arrow has an “image arrow” in its neighboring intermediate-parameter rectangle. The image arrow has the same shape as its original. The direction of the image arrow represents the requirement of the desired performance of the original parameter on the corresponding intermediate parameter. For example, fast tuning speed requires large loop bandwidth (BW), and, therefore, the image of the tuning speed arrow in the loop BW rectangle is also up-pointing. As another example, the image of the down-pointing arrow for reference feed-through spurs is up-pointing. The change in the arrow direction reflects the fact that low feed-through spurs require relatively high reference frequency.

The image arrows can have “child” image arrows in neighboring intermediate parameter rectangles, just as the performance parameter arrows have image arrows. Again, the shape of the child image arrow is the same as the corresponding “parent” image arrow while they may be different in direction. For example, the up-pointing loop BW arrow has a child image in the fref rectangle with the same direction because large loop BW requires high fref Likewise, the down-pointing phase noise floor arrow has an image in the same rectangle with an opposite direction.

The multiplication symbol “Ä” symbolizes that phase noise spectrum is, loosely speaking, the result of the phase noise floor being “multiplied” by the closed loop transfer function. The division symbol with an arrow pointing to the ref feedthrough rectangle symbolizes that the spur size is affected by how far away the spur is from the boundary of the pass band of the closed loop transfer function. The previously discussed trade-off’s are reflected by the four arrows in the fref rectangle. In this rectangle, the arrow corresponding to the step size is down-pointing while the other three, which are the image or “grand images” of the other three performance parameters, are up-pointing.

With integer N frequency synthesis, it is relatively easy to achieve rather good performance on any single parameter, if the other parameters are disregarded. Also, we can achieve the following combinations at certain costs. (1) small step size and low phase noise (at least at relatively high offset frequencies) at the cost of slow tuning speed. (2) fast tuning speed and low phase noise if large step size is allowed, (3) fast tuning speed and moderately small step size at the cost of high reference feedthrough spurs. However, it is difficult, if not possible at all, to have small step size, fast tuning speed, low phase noise, and low feedthrough spurs at the same time.

The advantages of fractional-N synthesizers

A close examination of the Figure 9 reveals that if we can somehow cut the tie between step size and fref, so that we can have both small step size and high fref at the same time, then the previously mentioned trade-off are eliminated. That is, if the down-pointing arrow in the fref rectangle is taken out, then there will not be any conflicting performance parameters. This is exactly what fractional-N synthesizers do. In fractional-N synthesis, especially with delta-sigma fractional-N , the choice of the reference frequency is almost completely independent of the step size since the latter is related to the former by,

Step size = fref/2^m (14)

where m is the number of bits in the input of the delta sigma modulator. For example, if one chooses fref to be 25 MHz, with an m of 20, a step size as small as 23.8 Hz can be achieved.

Obviously, the benefit of fractional-N is that all the desirable performance parameters, i.e., low phase noise, low reference feedthrough spurs, fast tuning speed, and small step size can be achieved at the same time, at least in theory. Low phase noise is simply the result of high reference frequency. With delta sigma fractional-N, the reference can be tens of MHz. Therefore, reference feedthrough spurs are simply not a concern at all. Also, the step size can be arbitrarily small. For example, a step size of less than 1 Hz has been reported while using a high fref [9]. Tuning speed is increased because of widened loop bandwidth. It can be further improved with some form of pre-tuning or fast lock feature included. For example, simulations show that a frequency jump of 50 MHz (settled to within 500 Hz) can be completed in about 50 us or less.

In addition, fractional-N synthesizers allow low cost external parts, i.e., VCO and capacitors in the loop filter. Since the VCO noise is suppressed within the loop bandwidth, wide loop bandwidth means VCO parts with high phase noise can be used without affecting the overall phase noise performance at the synthesizer output. Due to high reference frequency, the various current leakages, as previously discussed, are no longer a concern, meaning that low-leakage capacitors are not necessary.

Performance Parameters of Fractional-N Synthesizers and Related Design Issues

In the last section, we discussed the benefits that fractional-N can provide in theory. In actuality, some of these benefits are not fully realized depending on the architecture used. The purpose of this section is to discuss the possible performance deviation of a real fractional-N from the ideal case. At the end, we present a list of selection criteria for fractional-N.

Fractional spurs

These spurs appear at an offset frequency of 0.Ffref and possibly its harmonics, where 0.F is the fractional part of the division ratio. They occur in pairs, i.e., if it appears at an offset frequency f0 it will be seen at –f0 as well. Also, the pair of spurs at plus-minus 0.Ffref tend to be the highest. The behavior of fractional-N spurs are quite different between delta-sigma fractional-N and non-delta-sigma fractional-N, i.e., current injection based or fractional divider based fractional-N.

Fractional spurs in delta-sigma fractional-N

These spurs can be quite large within the loop bandwidth. For a given VCO frequency and hence a fixed value of 0.F, as we move outside of the loop bandwidth towards higher offset frequencies the spurs are suppressed significantly or are even completely gone. When the fractional spurs are “moved” away from the carrier by varying 0.F, they also decrease in size. Either way, the spurs appear to be attenuated quite effectively by the low pass action of the loop as in the case with phase noise on the reference.

To evaluate the performance on fractional spurs, it is advisable to “place” the fractional spurs as close to the carrier as possible and then gradually move them to higher offset frequencies outside the loop bandwidth. This can be done by choosing a VCO frequency close to an integer boundary of fref and then gradually “moving” the carrier away from the boundary. Note that one of the two highest spurs occurs at an integer boundary. The reason is that the boundary is 0.F fref away from the carrier.

The spur performance of delta-sigma fractional-N can be characterized by two parameters: the size of spurs within the loop bandwidth and how quickly they are attenuated as they are moved out of the loop bandwidth towards high offset frequencies. These two parameters determine the ratio of low spur to high spur bands of synthesized frequencies for a given application or standard. This can be understood with the use of Figure 10. The high spur bands (area C) are centered at each integer-N boundary. In a high spur band the synthesizer output has high spurious content close to the carrier, for example –55 dBc at a 10 KHz offset frequency. This area may or may not be useful depending on the application. In the low spur band (area A), fractional spur levels meet the desired specifications or are below the phase noise floor. In area B, the spur level transitions from the low spur region to the high spur region at a rate of x dB/dec which is determined by the closed loop transfer function of the PLL.

Figure 10 High spur bands

As an example, if a given application used a 20 MHz reference and a 20 KHz PLL loop bandwidth, and it was determined that the spur levels inside the loop bandwidth at integer-N boundaries were too high, the percentage of useable bandwidth, which meets the spurious specification for the application, would be [(20 -- 0.02) / 20] x100 % = 99.8 %.

A number of factors are thought to be the possible causes of fractional spurs in delta-sigma fractional-N. These include the operation of the delta-sigma modulator, the coupling between the PD/CP and the outside world through the power supply line or substrate, the nonlinearity of the charge pump, and divider kick-back to the VCO.

Fractional spurs in non-delta-sigma fractional-N synthesizers

The major difference between non-delta-sigma fractional-N and delta-sigma fractional-N is that for non-delta-sigma fractional-N the spurs tend to appear in the entire frequency range between two adjacent integer boundaries of fref. The primary cause for the spurs in this case is the imperfect quantization phase error cancellation, be it by use of fractional frequency division or by current injection.

Degradation of PD/CP noise floor

One of the advantages of fractional-N synthesis is its low phase noise as a result of high fref and, therefore, small frequency division ratio N.F. Referring back to Equation (12), we know that this is true only if the PD/CP noise floor is kept at the same level. In reality, the part of circuitry included in a fractional-N synthesizer to realize fractional-N frequency synthesis can cause this noise floor to rise. The degree of PD/CP noise floor degradation depends on the architecture used and circuit implementation.

In current injection based fractional-N, any noise on the compensation current can increase the noise floor. In fractional divider based fractional-N, phase noise on the output of the delay stages in the delay line can be a primary reason for noise floor increase. In the case of delta-sigma fractional-N, nonlinearity in the PD/CP may give rise to significant noise floor increase. The nonlinearity causes the high-frequency quantization noise to be mixed down into the base band. This actually poses an additional constraint in the PD/CP design for delta-sigma fractional-N synthesizers. That is, the designers need to worry about linearity and noise at the same time.

It is a straightforward matter to find out whether PD/CP noise floor us degraded by fractional division or not provided that the fractional-N synthesizer also supports an integer-N operation mode. This can be done by switching between fractional-N and integer-N modes and noting the difference in phase noise. This difference is a measure of the noise floor degradation. If there is no degradation the design has been successful. The integer division ratio used in the integer-N mode should be close to the non-integer division ratio. In this way, the variation on phase noise floor due to the frequency division ratio change can be ignored.

Fractionality

In non-delta-sigma fractional-N, fractionality is given as a set of fractional moduli or fractional denominators. For example, if 15 is given as one of the supported fractional moduli, the fractional part of the non-integer division ratio can be 1/15, 2/15, 3/15, … 14/15. In delta-sigma fractional-N, fractionality is characterized by the number of bits in the input to the delta sigma modulator. For example, if the modulator is 20-bit, then the fractional part of the division ratio is given by k/220, where k is an integer number between 1 and 220-1. In the language of non-delta-sigma fractional-N, the fractional modulus supported is 1/(220). The fractionality should be high enough (i.e., the supported fractional denominator is large enough) in order to achieve the desired step size and the phase noise floor at the same time. Otherwise, the trade-off between the step size and the phase noise floor as with traditional integer-N, is still present. Also, the fractionality should be appropriated for the crystal frequency used and the application. This is not a concern, however, if the fractional-N synthesis is delta-sigma modulator based and if the number of bits in the modulator is sufficiently large.

Tuning Speed

It is often thought that tuning speed is not a concern with fractional-N synthesis. However, if fractionality is not high enough, requiring the use of a low reference frequency, then the resulting narrow BW may yield a slow tuning speed. This is, however, probably not the case with delta-sigma fractional-N synthesizers where fractionality can be easily made large. In this case, the need to suppress quantization noise restricts the loop BW to some reasonable portion of fref, which sets a practical limit on the tuning speed. However, as fref can be in the order of tens of MHz, in general, the tuning speed is much higher than that for integer-N synthesizers.

List of selection criteria unique to fractional-N

When it comes to selecting a fractional-N supplier, one may want to check the following items in addition to the criteria applicable to integer-N synthesizers.

The type of fractional-N, i.e., is it delta sigma fractional-N or non-delta-sigma fractional-N.

The magnitude of in-band fractional spurs, the ratio of usable band over non-usable band, temperature and supply voltage dependence of the fractional-N spurs.

The degree of CP/PD noise floor degradation, and whether it is dependent on temperature.

Fractionality: is it sufficient to deliver the required step size, the desired speed and phase noise floor at the same time. Power consumption increase needed to realize fractional-N frequency synthesis.

Maximum reference frequency allowed.

The first item is important because the spur behavior, the degree of CP/PD noise degradation, and the fractionality could be quite different between the two types of fractional-N.

Summary

Fractional-N synthesizers allow the frequency step size to be a fraction of the reference frequency. This makes it possible to achieve, low phase noise, small (ppm) step size, fast tuning speed and minimal reference feedthrough spurs at the same time. There are a number of ways of achieving fractional-N frequency synthesis. So far, delta sigma modulator based fractional N synthesizers have emerged as the most successful technique to achieve all performance requirements at once. The high quantization noise at high frequencies can be readily filtered out by the low-passing filtering function of the loop. Fractional spurs can still be a problem in delta-sigma fractional-N synthesizers, but normally this problem persists only over very narrow and predictable bands. This together with other performance parameters should be examined when it comes to selecting a fractional-N supplier.

References

1. J.Gibbs and R. Temple, “Frequency Domain Yields Its Data to Phase-Locked Loop Synthesizer”, Electronics, PP. 107-113, April, 1978.

2. Razavi Behzad, RF Microelectronics, pp. 277-280, NJ: Prentice Hall PTR, 1998.

3. G.C.Gillette, “Digiphase Principle”, Frequency Technology, August, 1969.

4. J.Franca, Y.Tsividis (editors), Design of Analog-Digital VLSI Circuits for Telecommunications and Signal Processing, Chapter 17. Prentice Hall, 1993.

5. T.A.D. Riely and M.A.Copeland, and T.A.Kwasniewski, “Sigma Delta Modulation in Fractional-N Frequency Synthesis,” IEEE J.of Solid-State Circuits, Vol. 28, pp.553-559, May 1993.

6. Private communication with A.M.Fahim and M.I.Elmasry.

7. W.F. Egan, Frequency Synthesis by Phase Lock, New York: John Wiley, 1981.

8. Dean Banerjee, PLL Performance, Simulation, and Design, National Semiconductors, 1998.

9. T.P.Kenny, T.A.D.Riley, N.M.Filiol, and M.A.Copeland, “Design and Realization of a Digital Delta-Sigma Modulator for Fractional-N Frequency Snythesis”, IEEE Transactions on Vehicular Technology, Vol.48, pp, 510-522, March 1999.