The best introduction to PLL Design in my opinion is the book by Dean Banerjee.
Unlocking the Phase Lock Loop – Part 1
Fractional/Integer-N PLL Basics
Application Examples for CDCUx877x PLL family
Phase Lock Loop (PLL) Clock Control
A Fast Locking Scheme for PLL Frequency Synrhesizers
Predicting the Phase Noise and Jitter of PLL-Based Frequency …
Modeling Jitter in PLL-based Frequency Synthesizers
“TLC2932 PLL Building Block w/ Analog Voltage-Controlled Oscillator”
PROGRAMMABLE 2-PLL VCXO CLOCK SYNTHESIZER WITH 1.8-V, 2.5-V and …
Frequency-Modulated PLL Impact on Controller Area Network (CAN …
Phase Locked Loops-2/99
PLL-FM MODULATOR SUITABLE FOR MOBILE AND RADIO COMMUNICATION …
Spectral PLL Built-In Self-Test for Integrated RF-Transceivers
Actual PLL Packages
PLLCore, Quartus II 8.1 Handbook, Volume 5
Understanding PLL Timing for Stratix II Devices
Simulation Results of Phase Noise of PLL Functional Blocks in 0.35 …
Fast-lock Hybrid PLL Combining Fractional- & Integer-N Modes of Di …
21.9 – A Fully Integrated BiCMOS PLL for 60GHz Wireless Applications
10 Watt PLL Amplifer Section
Migration and deposition of PLL-g-PEG molecules along AFM probe tips
Design of an integrated CMOS PLL frequency synthesizer
On-Line Musical Beat Tracking with Phase-Locked-Loop (PLL) Technique
EUSAR 2002 GUIDELINES FOR CAMERA-READY PAPER TYPING AND SUBMISSION
Report on the Review of the LARP/CERN LHC Tune PLL Feedback …
Molecular weight determination of an optically active …
A multiple-crystal interface PLL with VCO realignment to reduce …
for their germline origin mutations in T-PLL on diverse haplotypes …
Optimizing VCO PLL Evaluations &PLL Synthesizer Designs
A Fully Integrated 48-GHz Low-Noise PLL with a Constant Loop Bandwidth
A Fully Integrated 48-GHz Low-Noise PLL with a Constant Loop Bandwidth
A Tracking PLL with an FIR Loop Filter
PROGRAMME 4: PROVINCIAL AND LOCAL LIAISON (PLL)
Integrating The PLL System On A Chip by Dean Banerjee, National …
PERFORMING TRANSIENT ANALYSIS ON PLL FREQUENCY SYNTHESIZERS
Translocation t(12;16)(ql3;pll) in Myxoid Liposarcoma and Round …
Session 1 PLL Session 1 PLL Fully integrated, high performance …
3.3 GHz LO + PLL-chip ATR2807 Summary Preliminary
Xilinx DS622 Phase Locked Loop (PLL) Module (v1.00a), Data Sheet
ICS502 LOCO PLL Clock Multiplier
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