By Louis Fan Fei, Garmin International
To meet the demands for the multi-band, multi-mode wireless standards in the current market, a highly integrated wireless receiver (RX) is desired. CMOS technology has become the technology of choice for the integrated receiver design. CMOS’s raw performance is not as good as SiGe or GaAs. But most of the baseband (BB) ICs are implemented with CMOS. Thus, it gives the advantage to CMOS in applications where a single chip that combines RF and BB IC is desired. The cost advantages of established CMOS manufacturing processes are also a factor to consider.
A traditional heterodyne RX converts the RF signal to the intermediate frequency (IF) stage. At every stage, various filters, such as surface acoustic wave (SAW) ones, are used to filter out the image signal, to select the channel, and to reduce the effects of any interfering signals. It is hard to achieve a fully-integrated receiver because of the required external components. Direct-conversion RX has become the dominant RX architecture. The well-known problems with a direct conversion RX like DC offset, high input second order intercept point (IIP2), and 1/f noise can be resolved with various correction loops in the BB and careful RFIC designs.
The major RX performance parameters are RX sensitivity, RX selectivity, dynamic range, IIP2, IIP3, and phase noise. The RX sensitivity is mostly set by the front end low noise amplifier (LNA) and the demodulator (DEMOD). The RX selectivity is determined by the on-chip low pass filter (LPF)’s rejection performance. Dynamic range, IIP2, and IIP3 are the measures of how robust a RX is with the presence of in-band and out-of-band interferences. Phase noise has a major impact on the signal modulation and demodulation as phase-shift key modulation is commonly used. This article thus will focus the major building blocks in the RX that influence receiver performance.
1. CMOS LNA.
A LNA’s noise figure (NF) and gain performance are the most dominant factors in the RX’s sensitivity. It is difficult to achieve the best performance of one parameter without sacrificing the other. The gain and NF compromise is a classical tradeoff. A single ended and a differential version of the popular LNA designs are shown in Figure 1.
The Miller multiply effect increases the parasitic capacitance at the gate of the LNA. A Cascode topology reduces this effect by stacking a common gate (CG) stage on a common source (CS) gain stage. The input and output port are better isolated to reduce the parasitic capacitance between the gate and the drain. In Figure 1a, M1is the CS stage while M2 is the CG stage. L1 is the degenerated feedback element to bring the input NF circle and the gain circle closer. Thus a compromise between the NF and the gain can be reached. L3 is the input matching element. C1 is the input DC block. The LNA is biased in a current mirror configuration with M3, I1, and R1. In a highly integrated IC circuit, the common mode noise is a major problem.
A differential circuit is often used to combat this problem. The differential LNA is presented in Figure 1b. It can be considered as two single-ended LNAs with the tail bias current. The tail current out of the M7 is important to reduce the common mode noise. Without it, there will not be enough common mode degenerated resistance to reduce the common mode noise. The bias current is set by the current mirror made from M6 and M7. It in turn sets the Vgs of M1 and M2. The drain voltage of M7 is set by the current mirror biasing at the gate of the M1 and M2.
2. CMOS DEMOD
A demodulator is used to convert an RF signal to the baseband. Since most modern wireless devices require both I and Q channels, two double balanced mixers (DBM) are needed in the DEMOD. The implementation is illustrated in Figure 2. M1 to M6 is the DBM for I channel. M11 to M16 is the DBM for Q channel. Since the same DBM is used for both I and Q channel, only one DBM is discussed in details. The incoming RF signal is amplified first by the gain stage such as M1 and M2. M3 to M6 are the switching FETs. It fundamentally serves the purpose of a multiply operation. In half the cycle, M3 and M6 are on. Local oscillator (LO) and RF are essentially multiplied in phase. In the other half the cycle, M4 and M5 are turned on to reverse the polarity of the output signal. The output loads are implemented with resistor R1 to R4. The degenerated feedback inductor L1 to L4 helps the IIP3 performance. The biasing is done with thediode connected FETs.
3a. Variable transconductance AGC
3b. Variable biasing AGC
There are many automatic gain control (AGC) topologies to choose from. The variable transconductance and the variable biasing AGC are the most popular for high-frequency operation. The variable transconductance circuit is shown in Figure 3a. It is based on the principle that the transconductance of the FET changes as the FET goes from a saturation mode to a triode mode. Thus, the gain is varied. M1 to M4 can be considered as the typical differential cascode gain stage. The difference is that Vcont is applied at the gates of M3 and M4. As Vcont decreases, the drain voltage at M1 and M2 drops. Eventually M1 and M2 enters the triode region as Vcont is lowered to below Vgs1+Vs1-Vt. M7 to M10 are the current source type load. Thus a common mode feedback (CMFB) is needed to make sure the current source matches with the current sink I1. The common mode voltage is sampled at the drain of M3 and M4 with M5 and M6. M5 and M6 can be considered as two large value resistors. They have the same value.
The sampled voltage is fed to a comparator (M11 to M14). The reference is fed to one input M14 while the sampled common mode is fed to the other input M13. The error voltage is used to control the bias current out of the current source M8 and M9. (M8 and M9 are the current bleeding path.) The closed feedback loop ensures correct bias current follows with the desired reference voltage.
A variable current AGC is based on the idea that the tranconductance of a FET changes with the bias current. By varying the bias current in the FET, the AGC can be accomplished. Such an implementation is presented in Figure 3b. M1 and M2 are the input gain buffer. M4 and M5 are the current bleeding path. If Vcont is larger than the Vref, more bias current flows through M3 and M6. In this mode, a high gain is expected. When the Vcon is reduced, more bias current flows through M4 and M5, the gain is thus reduced. M7 and M8 are the output emitter follower buffers to reduce output impedance. R1 is the degenerated resistor to improve the linearity of the AGC.
4a. NMOS only VCO.
4b. Complementary CMOS VCO
The CMOS VCO is based on the negative resistance theory. The Negative Metal Oxide Semiconductor (NMOS)-only version is presented in Fig 4a. By cross coupling M1 and M2, a positive feedback is created in the circuit. Looking into the gate of M1 and M2, a negative resistance can be expected. The operating frequency is set by the resonant tank. L1 and L2 provide the inductance part. The frequency can be tuned coarsely by the capacitance banks and fine tuned with the varactor caps. In Fig 4a, two bit 4 states capacitance banks are used. More banks can be added if a larger process variation is expected. By turning on/off M7 and M8, more/less total capacitance can be expected in the resonator tank. The varactor is implemented with FETs M5 and M6 by tying the source and the drain. M3 and M4 are the output buffers. Complementary CMOS VCO is presented in figure 4b. The key change is to add a cross-coupled Positive-Channel Metal Oxide Semiconductor (PMOS) pair. By adding a PMOS pair, two more elements are added to contribute the negative resistance while the bias current remains the same. So it is more power efficient.
The topologies presented are generic enough to be used in most wireless standards. They can be considered as a good starting point for your next CMOS RX design.
References
1. Behzad Razavi, "RF Microelectronics", Prentice-Hall, 1998.
2. Randall L. Geiger, Phillip E. Allen, Noel R. Strader, "VLSI design techniques for analog and digital circuits", McGraw-Hill, 1990.
3. Behzad Razavi, "Design of Analog CMOS Integrated Circuits", McGraw-Hill, 2001.
4. Thomas H. Lee, "The Design of CMOS Radio-Frequency Integrated Circuits", Cambridge University Press, 2004.
5. Allen Podell, RFIC Design and Applications, Besser Associates short course.
6. James Young, RF CMOS Design, Besser Associates short course.
7. John W. Rogers, "Radio Frequency Integrated Circuit Design", Artech House, 2003.
8. Ulrich L. Rohde, David P. Newkirk, "RF/Microwave Circuit Design for Wireless Applications", John Wiley & Sons, Inc., 2000.
9. Jan Crols, Michiel Steyaert, "CMOS Wireless Transceiver Design," Kluwer Academic Publishers, 2003.
10. Louis Fan Fei, "Subharmonic Mixer IC designs and enhancement techniques", Microwave Journal, Sep. 2005.
11. Louis Fan Fei, "CMOS Oscillator Design Considerations", Microwave Journal, April, 2007.
12. Louis Fan Fei, "CMOS AGC Design Strategies", TBD.
About the Author
Louis Fan Fei is currently an RF engineer at Garmin International where he designs GPS receivers since 2003. He worked on WLAN and wireless local loop circuits at Lucent/Agere System from 1998 to 2003. He also worked on microwave instrument circuit for HP/Agilent in Colorado Springs in the summer of 1997. He has more than 17 technical publications. He received his BEE and MSEE from Georgia Tech in 1996 and 1998, respectively.
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